MT28F320J3 Micron, MT28F320J3 Datasheet - Page 21

• Manufacturer Part Number: MT28F320J3
• Description: Q-FLASHTM MEMORY
• Manufacturer: Micron

128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
HIGH-Z
WHEN
BUSY?
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ISMS
7
STATUS REGISTER BITS
SR0 = RESERVED FOR FUTURE ENHANCEMENTS
SR7 = WRITE STATE MACHINE STATUS (ISMS)
SR6 = ERASE SUSPEND STATUS (ESS)
SR5 = ERASE AND CLEAR LOCK BITS STATUS (ECLBS)
SR4 = PROGRAM AND SET LOCK BIT STATUS (PSLBS)
SR3 = PROGRAMMING VOLTAGE STATUS (V
SR2 = PROGRAM SUSPEND STATUS (PSS)
SR1 = DEVICE PROTECT STATUS (DPS)
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Block Erasure or Clear Lock Bits
0 = Successful Block Erase or Clear Lock Bits
1 = Error in Programming or Setting Block Lock Bits
0 = Successful Program or Set Block Lock Bits
1 = Low Programming Voltage Detected,
0 = Programming Voltage OK
1 = Program Suspended
0 = Program in Progress/Completed
1 = Block Lock Bit Detected, Operation Aborted
0 = Unlock
ESS
6
Operation Aborted
ECLBS
5
Status Register Definitions
PSLBS
4
Table 16
21
PENS
V
PENS
3
)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOTES
Check STS or SR7 to determine block
erase, program, or lock bit
configuration completion. SR6–SR0 are
not driven while SR7 = 0.
If both SR5 and SR4 are “1s” after a
sequence was entered.
SR3 does not provide a continuous
programming voltage level indication.
The ISM interrogates and indicates the
programming voltage level only after
block erase, program, set block lock
bits, or clear block lock bits command
sequences.
SR1 does not provide a continuous
indication of block lock bit values. The
ISM interrogates the block lock bits
only after block erase, program, or lock
bit configuration command sequences.
It informs the system, depending on
the attempted operation, if the block
lock bit is set. Read the block lock
configuration codes using the READ
IDENTIFIER CODES command to
determine block lock bit status. SR0 is
reserved for future use and should be
masked when polling the status
register.
block erase or lock bit configuration
attempt, an improper command
PSS
2
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
DPS
1
©2002, Micron Technology, Inc.
R
0