MT28F320J3 Micron, MT28F320J3 Datasheet - Page 37

• Manufacturer Part Number: MT28F320J3
• Description: Q-FLASHTM MEMORY
• Manufacturer: Micron

REDUCING OVERSHOOTS AND UNDER-
SHOOTS WHEN USING BUFFERS OR
TRANSCEIVERS
input signals to exceed Flash memory specifications as
faster, high-drive devices such as transceivers or buff-
ers drive input signals to Flash memory devices. Many
buffer/transceiver vendors now carry bus-interface
devices with internal output-damping resistors or
reduced-drive outputs. Internal output-damping
resistors diminish the nominal output drive currents,
while still leaving sufficient drive capability for most
applications. These internal output-damping resistors
help reduce unnecessary overshoots and undershoots
by diminishing output-drive currents. When consider-
ing a buffer/transceiver interface design to Flash, de-
vices with internal output-damping resistors or re-
duced-drive outputs should be used to minimize over-
shoots and undershoots.
V
ranges, or RP# is not set to V
and lock bit configuration are not guaranteed. If RP#
transitions to V
bit configuration, STS (in default mode) will remain
LOW for a maximum time of
RESET operation is complete and the device enters
reset/power-down mode. The aborted operation may
leave data partially corrupted after programming, or
partially altered after an erase or lock bit configuration.
Therefore, BLOCK ERASE and LOCK BIT CONFIGURA-
TION commands must be repeated after normal op-
eration is restored. Device power-off or RP# = V
the status register. The CEL latches commands issued
by system software and is not altered by V
transitions, or ISM actions. Its state is read array mode
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
CC
Overshoots and undershoots can sometimes cause
If V
, V
PEN
PEN
or V
, RP# TRANSITIONS
CC
IL
falls outside of the specified operating
during block erase, program, or lock
t
IH
PLPH +
, block erase, program,
t
PHRH, until the
PEN
IL
or CEx
clears
37
upon power-up, upon exiting reset/power-down
mode, or after V
kept at or above V
and after V
placed in read array mode via the READ ARRAY com-
mand if subsequent access to the memory array is de-
sired. During V
below V
POWER-UP/DOWN PROTECTION
protection against accidental block erasure, program-
ming, or lock bit configuration. Internal circuitry resets
the CEL to read array mode at power-up. A system
designer must watch out for spurious writes for V
voltages above V
must be LOW and the device enabled (see Table 2) for
a command write, driving WE# to V
device inhibits WRITEs. The CEL’s two-step command
sequence architecture provides added protection
against data alteration. In-system block lock and un-
lock capability protects the device against inadvertent
programming. The device is disabled when RP# = V
regardless of its control inputs. Keeping V
V
POWER DISSIPATION
tion not only during device operation, but also for data
retention during system idle time. Flash memory’s
nonvolatility increases usable battery life because data
is retained when system power is removed.
PENLK
After block erase, program, or lock bit configuration,
During power transition, the device itself provides
Designers must consider battery power consump-
prevents inadvertent data change.
CC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
.
PEN
PEN
transitions to V
CC
LKO
PEN
128Mb, 64Mb, 32Mb
transitions below V
transitions, V
when V
during V
Q-FLASH MEMORY
PEN
CC
PENLK
is active. Because WE#
PEN
transitions.
, the CEL must be
must be kept at or
IH
LKO
or disabling the
©2002, Micron Technology, Inc.
. V
CC
PEN
must be
below
CC
IL