IDT72V2101L10PF IDT, Integrated Device Technology Inc, IDT72V2101L10PF Datasheet - Page 11

• Manufacturer Part Number: IDT72V2101L10PF
• Description: IC FIFO SS 131X18 10NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V2101L10PF

• Function: Synchronous
• Memory Size: 2.3K (131 x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V2101L10PF

SERIAL PROGRAMMING MODE
programming of PAE and PAF values can be achieved by using a
combination of the LD, SEN, WCLK and SI input pins. Programming PAE
and PAF proceeds as follows: when LD and SEN are set LOW, data on the
SI input are written, one bit for each WCLK rising edge, starting with the
Empty Offset LSB and ending with the Full Offset MSB. A total of 36 bits
for the IDT72V2101 and 38 bits for the IDT72V2111. See Figure 13, Serial
Loading of Programmable Flag Registers, for the timing diagram for this
mode.
selectively. PAE and PAF can show a valid status only after the complete
set of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered.
When LD is LOW and SEN is HIGH, no serial write to the registers can
occur.
programming sequence. In this case, the programming of all offset bits
does not have to occur at once. A select number of bits can be written to
the SI input and then, by bringing LD and SEN HIGH, data can be written
to FIFO memory via D
LD and SEN restored to a LOW, the next offset bit in sequence is written
to the registers via SI. If an interruption of serial programming is desired,
it is sufficient either to set LD LOW and deactivate SEN or to set SEN LOW
and deactivate LD. Once LD and SEN are both restored to a LOW level,
serial offset programming continues.
valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves the above
criteria; PAF will be valid after two more rising WCLK edges plus t
will be valid after the next two rising RCLK edges plus t
PARALLEL MODE
programming of PAE and PAF values can be achieved by using a combination
of the LD, WCLK , WEN and Dn input pins.
set LOW, data on the inputs Dn are written into the Empty Offset LSB Register
on the first LOW-to-HIGH transition of WCLK. Upon the second LOW-to-HIGH
transition of WCLK, data are written into the Empty Offset Mid-Byte Register.
Upon the third LOW-to-HIGH transition of WCLK, data are written into the Empty
Offset MSB Register. Upon the fourth LOW-to-HIGH transition of WCLK, data
are written into the Full Offset LSB Register. Upon the fifth LOW-to-HIGH
transition of WCLK, data are written into the Full Offset Mid-Byte Register. Upon
the sixth LOW-to-HIGH transition of WCLK, data are written into the Full Offset
MSB Register. The seventh transition of WCLK writes, once again, into the
Empty Offset LSB Register. See Figure 14, Parallel Loading of Programmable
Flag Registers, for the timing diagram for this mode.
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
should not be performed simultaneously to the offset registers. A Master Reset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers.
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
If Serial Programming mode has been selected, as described above, then
Using the serial method, individual registers cannot be programmed
Write operations to the FIFO are allowed before and during the serial
From the time serial programming has begun, neither partial flag will be
It is not possible to read the flag offset values in a serial mode.
If Parallel Programming mode has been selected, as described above, then
The act of writing offsets in parallel employs a dedicated write offset register
Programming PAE and PAF proceeds as follows: when LD and WEN are
TM
n
262,144 x 9, 524,288 x 9
by toggling WEN. When WEN is brought HIGH with
PAE
plus t
PAF
SKEW2
, PAE
.
11
programming sequence. In this case, the programming of all offset registers does
not have to occur at one time. One, two or more offset registers can be written
and then by bringing LD HIGH, write operations can be redirected to the FIFO
memory. When LD is set LOW again, and WEN is LOW, the next offset register
in sequence is written to. As an alternative to holding WEN LOW and toggling
LD, parallel programming can also be interrupted by setting LD LOW and
toggling WEN.
programming process. From the time parallel programming has begun, a partial
flag output will not be valid until the appropriate offset word has been written to
the register(s) pertaining to that flag. Measuring from the rising WCLK edge that
achieves the above criteria; PAF will be valid after two more rising WCLK edges
plus t
t
register pointer. The contents of the offset registers can be read on the Q
Q
LSB Register on the first LOW-to-HIGH transition of RCLK. Upon the second
LOW-to-HIGH transition of RCLK, data are read from the Empty Offset Mid-Byte
Register. Upon the third LOW-to-HIGH transition of RCLK, data are read from
the Empty Offset MSB Register. Upon the fourth LOW-to-HIGH transition of
RCLK, data are read from the Full Offset LSB Register. Upon the fifth LOW-
to-HIGH transition of RCLK, data are read from the Full Offset Mid-Byte Register.
Upon the sixth LOW-to-HIGH transition of RCLK, data are read from the Full
Offset MSB Register. The seventh transition of RCLK reads, once again, from
the Empty Offset LSB Register. See Figure 15, Parallel Read of Programmable
Flag Registers, for the timing diagram for this mode.
writes to the FIFO. The interruption is accomplished by deasserting REN, LD,
or both together. When REN and LD are restored to a LOW level, reading of
the offset registers continues where it left off. It should be noted, and care should
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
which timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT OPERATION
accessed again. There are two stages: first, a setup procedure that resets
the read pointer to the first location of memory, then the actual retransmit,
which consists of reading out the memory contents, starting at the beginning
of memory.
edge. REN and WEN must be HIGH before bringing RT LOW. At least two
words, but no more than D - 2 words should have been written into the FIFO
and read from the FIFO between Reset (Master or Partial) and the time of
Retransmit setup. D = 262,144 for the IDT72V2101 and D = 524,288 for the
IDT72V2111 in IDT Standard mode. In FWFT mode, D = 262,145 for the
IDT72V2101 and D = 524,289 for the IDT72V2111.
Retransmit setup by setting EF LOW. The change in level will only be noticeable
if EF was HIGH before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
SKEW2
n
pins when LD is set LOW and REN is set LOW.
Write operations to the FIFO are allowed before and during the parallel
Note that the status of a partial flag (PAE or PAF) output is invalid during the
The act of reading the offset registers employs a dedicated read offset
For the IDT72V2101/72V2111, data is read via Q
It is permissible to interrupt the offset register read sequence with reads or
The Retransmit operation allows data that has already been read to be
Retransmit setup is initiated by holding RT LOW during a rising RCLK
If IDT Standard mode is selected, the FIFO will mark the beginning of the
Parallel reading of the offset registers is always permitted regardless of
PAF
.
, PAE will be valid after the next two rising RCLK edges plus t
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
n
from the Empty Offset
PAE
plus
0
-