IDT72V2101L10PF IDT, Integrated Device Technology Inc, IDT72V2101L10PF Datasheet - Page 3

• Manufacturer Part Number: IDT72V2101L10PF
• Description: IC FIFO SS 131X18 10NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V2101L10PF

• Function: Synchronous
• Memory Size: 2.3K (131 x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V2101L10PF

memory. (See Table I and Table II.) Programmable offsets determine the flag
switching threshold and can be loaded by two methods: parallel or serial. Two
default offset settings are also provided, so that PAE can be set to switch at 127
or 1,023 locations from the empty boundary and the PAF threshold can be set
at 127 or 1,023 locations from the full boundary. These choices are made with
the LD pin during Master Reset.
WCLK, are used to load the offset registers via the Serial Input (SI). For
parallel programming, WEN together with LD on each rising edge of WCLK,
are used to load the offset registers via D
rising edge of RCLK can be used to read the offsets in parallel from Q
regardless of whether serial or parallel offset loading has been selected.
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode. The LD pin selects either a partial flag default
setting of 127 with parallel programming or a partial flag default setting of 1,023
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
FIRST WORD FALL THROUGH/SERIAL INPUT
PAE and PAF can be programmed independently to switch at any point in
For serial programming, SEN together with LD on each rising edge of
During Master Reset (MRS) the following events occur: The read and write
PROGRAMMABLE ALMOST-FULL (PAF)
FULL FLAG/INPUT READY (FF/IR)
TM
262,144 x 9, 524,288 x 9
Figure 1. Block Diagram of Single 262,144 x 9 and 524,288 x 9 Synchronous FIFO
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
SERIAL ENABLE(SEN)
n
. REN together with LD on each
DATA IN (D
PARTIAL RESET (PRS)
LOAD (LD)
(FWFT/SI)
0
- D
n
)
n
72V2101
72V2111
3
IDT
with serial programming. The flags are updated according to the timing mode
and default offsets selected.
location of the memory. However, the timing mode, partial flag program-
ming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the
timing mode and offsets in effect. PRS is useful for resetting a device in mid-
operation, when reprogramming partial flags would be undesirable.
on the RT input during a rising RCLK edge initiates a retransmit operation
by setting the read pointer to the first location of the memory array.
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
cron CMOS technology.
MASTER RESET (MRS)
The Partial Reset (PRS) also sets the read and write pointers to the first
The Retransmit function allows data to be reread from the FIFO. A LOW
If, at any time, the FIFO is not actively performing an operation, the chip will
The IDT72V2101/72V2111 are fabricated using IDT’s high speed submi-
READ CLOCK (RCLK)
READ ENABLE (REN)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF FULL FLAG (HF)
DATA OUT (Q
OUTPUT ENABLE (OE)
0
- Q
n
COMMERCIAL AND INDUSTRIAL
)
TEMPERATURE RANGES
4669 drw 03