IDT72V2101L10PF IDT, Integrated Device Technology Inc, IDT72V2101L10PF Datasheet - Page 2

• Manufacturer Part Number: IDT72V2101L10PF
• Description: IC FIFO SS 131X18 10NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V2101L10PF

• Function: Synchronous
• Memory Size: 2.3K (131 x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V2101L10PF

DESCRIPTION (CONTINUED)
(WEN) input. Data is written into the FIFO on every rising edge of WCLK when
WEN is asserted. The output port is controlled by a Read Clock (RCLK) input
and Read Enable (REN) input. Data is read from the FIFO on every rising edge
of RCLK when REN is asserted. An Output Enable (OE) input is provided for
three-state control of the outputs.
0 to f
frequency of the one clock input with respect to the other.
IDT Standard mode and First Word Fall Through (FWFT) mode.
appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating REN and enabling a
rising RCLK edge, will shift the word from internal memory to the data output lines.
PIN CONFIGURATIONS
NOTES:
1. DC = Don’t Care. Must be tied to GND or V
2. This pin may either be tied to ground or left open.
3. DNC = Do Not Connect.
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
The input port is controlled by a Write Clock (WCLK) input and a Write Enable
The frequencies of both the RCLK and the WCLK signals may vary from
In IDT Standard mode, the first word written to an empty FIFO will not
There are two possible timing modes of operation with these devices:
MAX
with complete independence. There are no restrictions on the
PIN 1
TM
262,144 x 9, 524,288 x 9
GND
GND
GND
GND
GND
GND
GND
GND
GND
WEN
DC
SEN
V
V
D8
D7
CC
CC
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
CC
, cannot be left open.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TQFP (PN64-1, order code: PF)
TOP VIEW
2
to the data output lines after three transitions of the RCLK signal. A REN
does not have to be asserted for accessing the first word. However,
subsequent words written to the FIFO do require a LOW on REN for access.
The state of the FWFT/SI input during Master Reset determines the timing
mode in use.
can provide, the FWFT timing mode permits depth expansion by chaining
FIFOs in series (i.e. the data outputs of one FIFO are connected to the
corresponding data inputs of the next). No external logic is required.
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and
FF functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespective of timing mode.
In FWFT mode, the first word written to an empty FIFO is clocked directly
For applications requiring more data storage capacity than a single FIFO
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
COMMERCIAL AND INDUSTRIAL
4669 drw 02
TEMPERATURE RANGES
DNC
DNC
GND
DNC
DNC
V
DNC
DNC
DNC
GND
DNC
DNC
Q8
Q7
Q6
GND
CC
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)