IDT72T20128L6-7BB IDT, Integrated Device Technology Inc, IDT72T20128L6-7BB Datasheet - Page 14

• Manufacturer Part Number: IDT72T20128L6-7BB
• Description: IC FIFO 1KX20 2.5V 6-7NS 208BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T20128L6-7BB

• Function: Synchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T20128L6-7BB

TABLE 3 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
PROGRAMMING FLAG OFFSETS
72T20108/72T20118/72T20128 have internal registers for these offsets.
There are four selectable default offset values during Master Reset. These offset
values are shown in Table 3. The offset values can also be programmed serially
into the FIFO. To load offset values, set SEN LOW and the rising edge of SCLK
NOTE:
1. See table 3 for values for n, m.
NOTE:
1. See table 3 for values for n, m.
2. Number of Words in FIFO = FIFO Depth + Output Register.
3. FWFT mode available only in Single Data Rate mode.
TABLE 5 ⎯ STATUS FLAGS FOR FWFT MODE
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
IW = OW = x10
IW
IW = OW = x20
IW = OW = x10
IW
IW = OW = x20
TABLE 4 ⎯ STATUS FLAGS FOR IDT STANDARD MODE
Number of
Words in
FIFO
Number of
Words in
FIFO
Full and Empty Flag offset values are user programmable. The IDT72T2098/
≠
≠
OW or
OW or
IDT72T2098, 72T20108, 72T20118, 72T20128
FSEL1
H
H
L
L
(16,386) to (32,764-(m+1))
(16,385) to (32,768-(m+1)) (32,769) to (65,536-(m+1))
(32,768-m) to 32,767
(32,764-m) to 32,768
IDT72T2098
IDT72T2098
1 to n
1 to n
32,768
32,769
0
0
(1)
(1)
FSEL0
H
H
L
L
(32,770) to (65,537-(m+1))
(65,536-m) to 65,535
(65,537-m) to 65,536
IDT72T20108
IDT72T20108
IDT72T2098
IDT72T2098
1 to n
65,536
1 to n
65,537
0
0
(1)
(1)
Offsets n,m
255
127
(65,538) to (131,073-(m+1))
63
(65,537) to (131,072-(m+1))
7
(131,073-m) to 131,072
(131,072-m) to 131,071
IDT72T20108
IDT72T20118
IDT72T20108
IDT72T20118
1 to n
131,073
1 to n
131,072
0
0
(1)
(1)
14
will load data from the SI input into the offset registers. SCLK runs at a nominal
speed of 10MHz at the maximum. The programming sequence starts with one
bit for each SCLK rising edge, starting with the Empty Offset LSB and ending
with the Full Offset MSB. The total number of bits per device is listed in Figure
3, Programmable Flag Offset Programming Sequence. See Figure 25,
Loading of Programmable Flag Registers, for the timing diagram for this mode.
The PAE and PAF can show a valid status only after the complete set of bits (for
all offset registers) has been entered. The registers can be reprogrammed as
long as the complete set of new offset bits is entered.
the current offset values. Similar to loading offset values, set SREN LOW and
the rising edge of SCLK will send data from the offset registers out to the SO output
port. When initializing a read to the offset registers, data will be read starting from
the first location in the register, regardless of where it was last read.
the control pins and sequence for programming offset registers and reading and
writing into the FIFO.
after Master Reset. Valid programming ranges are from 0 to D-1.
Figure 3, Programmable Flag Offset Programming Sequence, summarizes
The offset registers may be programmed (and reprogrammed) any time
In addition to loading offset values into the FIFO, it is also possible to read
(131,074) to (262,145-(m+1)) (262,146) to (524,289-(m+1))
(131,073) to (262,144-(m+1)) (262,145) to (524,288-(m+1))
(262,145-m) to 262,144
(262,144-m) to 262,143
IDT72T20118
IDT72T20128
IDT72T20118
IDT72T20128
1 to n
262,144
1 to n
262,145
0
0
(1)
(1)
(524,289-m) to 524,288
(524,288-m) to 524,287
IDT72T20128
IDT72T20128
524,289
524,288
1 to n
1 to n
COMMERCIAL AND INDUSTRIAL
0
0
(1)
(1)
TEMPERATURE RANGES
FEBRUARY 13, 2009
FF
IR
H
H
H
H
L
H
L
L
L
L
PAF PAE EF
PAF PAE OR
H
H
H
L
L
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
5996 drw05
L
H
H
H
H
H
L
L
L
L