IDT72T20128L6-7BB IDT, Integrated Device Technology Inc, IDT72T20128L6-7BB Datasheet - Page 18

• Manufacturer Part Number: IDT72T20128L6-7BB
• Description: IC FIFO 1KX20 2.5V 6-7NS 208BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T20128L6-7BB

• Function: Synchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T20128L6-7BB

PAF flags will not be updated. The write and read clocks can either be
independent or coincident.
WRITE ENABLE (WEN)
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read opera-
tion.
WCLK cycle.
inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH, allowing a write to occur. The FF is updated by two WCLK
cycles + t
further write operations. Upon the completion of a valid read cycle, IR will go
LOW, allowing a write to occur. The IR flag is updated by two WCLK cycles +
t
FWFT.
WRITE SINGLE DATA RATE (WSDR)
Single Data Rate mode. In this mode, all write operations are based only on
the rising edge of WCLK, provided that WEN and WCS are LOW. When
WSDR is HIGH, the read port will be set to Double Data Rate mode. In this
mode, all write operations are based on both the rising and falling edge of
WCLK, provided that WEN and WCS are LOW, on the rising edge of WCLK.
READ CLOCK (RCLK)
If the Read Single Data Rate (RSDR) pin is selected, data will be read only on
the rising edge of RCLK, provided that REN and RCS are LOW. If the RSDR
is not selected, data will be read on both the rising and falling edge of WCLK,
provided that REN and RCS are LOW, on the rising edge of RCLK. Setup and
hold times must be met with respect to the LOW-to-HIGH transition of the
RCLK. It is permissible to stop the RCLK. Note that while RCLK is idle, the EF/
OR and PAE flags will not be updated. Write and Read Clocks can be inde-
pendent or coincident.
READ ENABLE (REN)
output register on the rising edge of every RCLK cycle if the device is not
empty.
and no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
written to an empty FIFO, must be requested using REN provided that the
Read Chip Select (RCS) is LOW. When the last word has been read from the
FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations.
REN is ignored when the FIFO is empty. Once a write is performed, EF will go
HIGH allowing a read to occur. Both RCS and REN must be active LOW for
data to be read out on the rising edge of RCLK.
to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + t
after the first write. REN and RCS do not need to be asserted LOW for the First
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
SKEW
When the WEN input is LOW, data may be loaded into the FIFO RAM array
When WEN is HIGH, no new data is written in the RAM array on each
To prevent data overflow in the IDT Standard mode, FF will go LOW,
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting
WEN is ignored when the FIFO is full in either IDT Standard mode or
When the Write Single Data Rate pin is LOW, the write port will be set to
A read cycle is initiated on the rising and/or falling edge of the RCLK input.
When Read Enable is LOW, data is loaded from the RAM array into the
When the REN input is HIGH, the output register holds the previous data
In IDT Standard mode, every word accessed at Qn, including the first word
In FWFT mode, the first word written to an empty FIFO automatically goes
after the valid RCLK cycle.
SKEW
after the RCLK cycle.
SKEW
18
Word to fall through to the output register. All subsequent words require that a
read operation to be executed using REN and RCS. The LOW-to-HIGH
transition of RCLK after the last word has been read from the FIFO will make
Output Ready (OR) go HIGH with a true read (RCLK with REN and RCS
LOW), inhibiting further read operations. REN is ignored when the FIFO is
empty.
READ SINGLE DATA RATE (RSDR)
Single Data Rate mode. In this mode, all read operations are based only on
the rising edge of RCLK, provided that REN and RCS are LOW. When RSDR
is HIGH, the read port will be set to Double Data Rate mode. In this mode, all
read operations are based on both the rising and falling edge of RCLK,
provided that REN and RCS are LOW, on the rising edge of RCLK.
SERIAL CLOCK (SCLK)
registers. Data from the Serial Input (SI) can be loaded into the offset registers
on the rising edge of SCLK provided that SEN is LOW. Data can be read from
the offset registers via the Serial Output (SO) on the rising edge of SCLK
provided that SREN is LOW. The serial clock can operate at a maximum
frequency of 10MHz and its parameters are different than the FIFO system
clock.
SERIAL ENABLE (SEN)
mable offset registers. It is used in conjunction with SI and SCLK when pro-
gramming the offset registers. When SEN is LOW, data at the Serial In (SI)
input can be loaded into the offset register, one bit for each LOW-to-HIGH
transition of SCLK.
offsets are loaded. SEN functions the same way in both IDT Standard and
FWFT modes.
SERIAL READ ENABLE (SREN)
mable offset registers. It is used in conjunction with SI and SCLK when reading
from the offset registers. When SREN is LOW, data can be read out of the offset
register from the SO output, one bit for each LOW-to-HIGH transition of SCLK.
ever SREN is activated values in the offset registers are read starting from the
first location in the offset registers and not from where the last offset value was
read. SREN functions the same way in both IDT Standard and FWFT modes.
SERIAL IN (SI)
programmable offset registers. It is used in conjunction with the Serial Clock
(SCLK) and the Serial Enable (SEN). Data from this input can be loaded into
the offset register, one bit for each LOW-to-HIGH transition of SCLK provided
that SEN is LOW.
SERIAL OUT (SO)
offsets in the programmable offset registers. It is used in conjunction with the
Serial Clock (SCLK) and the Serial Enable Output (SREN). Data from the
offset register can be read out using this pin, one-bit for each LOW-to-HIGH
transition of SCLK provided that SREN is LOW.
When the Read Single Data Rate pin is LOW, the read port will be set to
The serial clock is used to load and read data in the programmable offset
The SEN input is an enable used for serial programming of the program-
When SEN is HIGH, the offset registers retain the previous settings and no
The SREN output is an enable used for reading the value of the program-
This pin acts as a serial input for loading PAE and PAF offsets into the
This pin acts as a serial output for reading the values of the PAE and PAF
When SREN is HIGH, the reading of the offset registers will stop. When-
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009