IDT72T20128L6-7BB IDT, Integrated Device Technology Inc, IDT72T20128L6-7BB Datasheet - Page 22

• Manufacturer Part Number: IDT72T20128L6-7BB
• Description: IC FIFO 1KX20 2.5V 6-7NS 208BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T20128L6-7BB

• Function: Synchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T20128L6-7BB

TABLE 7 — BUS-MATCHING WRITE TO READ RATIO (CONTINUED)
x20 DDR Input to x10 SDR Output
x20 SDR Input to x20 DDR Output
x10 SDR Input to x20 SDR Output
x10 SDR Input to x20 DDR Output
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
SDR Write Clock x10 Data In
Positive Edge 1
Positive Edge 2
SDR Write Clock x10 Data In
Positive Edge 1
Positive Edge 2
Positive Edge 3
Positive Edge 4
DDR Write Clock x20 Data In
Positive Edge 1
Positive Edge 1
Negative Edge 1 D[19:10] <= B3 Positive Edge 3
Negative Edge 1 D[9:0] <= B4 Positive Edge 4
SDR Write Clock x20 Data In
Positive Edge 1
Positive Edge 2
WSDR
WSDR
WSDR
WSDR
H
L
L
L
RSDR
RSDR
RSDR
RSDR
FOUR WRITE TO ONE READ (4:1)
H
H
L
L
Configuration
Configuration
Configuration
Configuration
D[19:10] <= B1 Positive Edge 1
D[9:0] <= B2
D[9:0] <= B1
D[9:0] <= B2
D[9:0] <= B3
D[9:0] <= B4
D[19:10] <= B1 Positive Edge 1
D[9:0] <= B2 Positive Edge 2
D[19:0] <= W1 Positive Edge 1
D[19:0] <= W2 Negative Edge 1 Q[19:0] <= W2
IW
IW
IW
IW
H
H
L
L
OW
OW
OW
OW
SDR Read Clock x20 Data Out
Positive Edge 1
DDR Read Clock x20 Data Out
Positive Edge 1
Positive Edge 1
Negative Edge 1 Q[19:0] <= B3
Negative Edge 1 Q[9:0] <= B4
SDR Read Clock x10 Data Out
DDR Read Clock x20 Data Out
L
L
L
L
ONE WRITE TO FOUR READ (1:4)
TWO WRITE TO ONE READ (2:1)
Q[19:10] <= B1
Q[9:0] <= B2
Q[19:10] <= B1
Q[9:0] <= B2
Q[9:0] <= B1
Q[9:0] <= B2
Q[9:0] <= B3
Q[9:0] <= B4
Q[19:0] <= W1
22
x10 DDR Input to x20 DDR Output
x10 SDR Input to x10 DDR Output
DDR Write Clock x10 Data In
Positive Edge 1
Negative Edge 1 D[9:0]
Positive Edge 2
Negative Edge 2 D[9:0]
DDR Write Clock x10 Data In
Positive Edge 1
Positive Edge 2
WSDR
WSDR
H
L
RSDR
RSDR
H
H
Configuration
Configuration
D[9:0]
D[9:0]
D[9:0]
D[9:0]
IW
IW
H
H
<= B1 Positive Edge 1
<= B2 Postive Edge 1
<= B3 Negative Edge 1 Q[19:10] <= B3
<= B4 Negative Edge 1 Q[9:0]
<= B1 Positive Edge 1
<= B3 Negative Edge 1 Q[9:0]
OW
OW
DDR Read Clock x20 Data Out
SDR Read Clock x10 Data Out
H
L
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009
Q[19:10] <= B1
Q[9:0]
Q[9:0]
<= B2
<= B4
<= B1
<= B3