IDT72T20128L6-7BB IDT, Integrated Device Technology Inc, IDT72T20128L6-7BB Datasheet - Page 48

• Manufacturer Part Number: IDT72T20128L6-7BB
• Description: IC FIFO 1KX20 2.5V 6-7NS 208BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T20128L6-7BB

• Function: Synchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T20128L6-7BB

WCLK
RCLK
WCLK
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
3. PAF is asserted and updated on the rising edge of WCLK only.
4. t
5. RCS = LOW.
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted and updated on the rising edge of RCLK only.
5. t
6. RCS = LOW.
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
RCLK
WEN
REN
WEN
PAF
REN
In IDT Standard mode: if x20 Input or x20 Output bus Width is selected, D = 32,768 for the IDT72T2098, 65,536 for the IDT72T20108, 131,072 for the IDT72T20118, 262,144 for
the IDT72T20128. If both x10 Input and x10 Output bus Widths are selected, D = 65,536 for the IDT72T2098, 131,072 for the IDT72T20108, 262,144 for the IDT72T20118, 524,288
for the IDT72T20128.
In FWFT mode: if x20 Input or x20 Output bus Width is selected, D = 32,769 for the IDT72T2098, 65,537 for the IDT72T20108, 131,073 for the IDT72T20118, 262,145 for the IDT72T20128.
If both x10 Input and x10 Output bus Widths are selected, D = 65,537 for the IDT72T2098, 131,073 for the IDT72T20108, 262,145 for the IDT72T20118, 524,289 for the IDT72T20128.
rising edge of RCLK and the rising edge of WCLK is less than t
PAE
rising edge of WCLK and the rising edge of RCLK is less than t
SKEW3
SKEW3
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
t
CLKH1
t
CLKL1
t
ENS
t
CLKL1
t
n words in FIFO
n + 1 words in FIFO
ENS
t
CLKL1
Figure 30. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
Figure 29. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
D - (m +1) words in FIFO
t
ENH
t
(2)
SKEW3
1
,
t
(3)
ENH
(4)
t
PAES
1
(2)
2
SKEW3
SKEW3
, then the PAF deassertion time may be delayed one extra WCLK cycle.
, then the PAE deassertion may be delayed one extra RCLK cycle.
2
48
t
PAFS
t
ENS
t
ENS
n + 1 words in FIFO
n + 2 words in FIFO
t
t
ENH
SKEW3
t
D - m words in FIFO
ENH
(2)
(3)
(3)
,
1
1
COMMERCIAL AND INDUSTRIAL
(2)
t
PAES
TEMPERATURE RANGES
PAES
2
PAFS
FEBRUARY 13, 2009
2
t
PAFS
). If the time between the
). If the time between the
n words in FIFO
n + 1 words in FIFO
D-(m+1) words
in FIFO
5996 drw33
5996 drw32
(2)
(2)
,
(3)