IDT72T20128L6-7BB IDT, Integrated Device Technology Inc, IDT72T20128L6-7BB Datasheet - Page 17

• Manufacturer Part Number: IDT72T20128L6-7BB
• Description: IC FIFO 1KX20 2.5V 6-7NS 208BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T20128L6-7BB

• Function: Synchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T20128L6-7BB

SIGNAL DESCRIPTION
INPUTS:
DATA IN (D0 – Dn)
data (D
CONTROLS:
MASTER RESET (MRS)
state. This operation sets the internal read and write pointers to the first location
of the RAM array. PAE will go LOW and PAF will go HIGH.
EF and FF are selected. EF will go LOW and FF will go HIGH, If FWFT is
HIGH, then the First Word Fall Through (FWFT) mode, along with IR and OR
are selected. OR will go HIGH and IR will go LOW.
defined during the Master Reset cycle.
Reset is required after power up before a write operation can take place. MRS
is asynchronous.
PARTIAL RESET (PRS)
state. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAM array. PAE goes LOW and PAF goes
HIGH.
after Partial Reset. If IDT Standard Mode is active, then FF will go HIGH and
EF will go LOW. If the First Word Fall Through mode is active, then OR will go
HIGH and IR will go LOW.
changed. The output register is initialized to all zeroes. PRS is asynchronous.
Partial Reset is useful for resetting the read and write pointers to zero without
affecting the values of the programmable flag offsets and the timing mode of the
FIFO.
RETRANSMIT (RT)
Together they provide a means by which data previously read out of the FIFO
can be reread any number of times. When the retransmit operation is selected
(i.e. after data has been marked), a rising edge on RCLK while RT is LOW will
reset the read pointer back to the memory location set by the user via the
MARK input.
rising edge of RCLK that retransmit was initiated (i.e. rising edge of RCLK
while RT is LOW). EF will go back to HIGH on the next rising edge of RCLK,
which signifies that retransmit setup is complete. The next read operation will
access data from the “marked” memory location.
pointer returning to the “marked” location. See Figure 23, Retransmit from
Mark in Double Data Rate Mode (IDT Standard Mode) for the relevant timing
diagram.
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
Data inputs for 20-bit wide data, (D
A Master Reset is accomplished whenever the MRS input is taken to a LOW
If FWFT is LOW during Master Reset then IDT Standard mode along with
All control settings such as OW, IW, WSDR, RSDR, FSEL0 and FSEL1 are
During a Master Reset the output register is initialized to all zeros. A Master
See Figure 8, Master Reset Timing, for the relevant timing diagram.
A Partial Reset is accomplished whenever the PRS input is taken to a LOW
Whichever mode was active at the time of Partial Reset will remain active
Following Partial Reset, all values held in the offset registers remain un-
See Figure 9, Partial Reset Timing, for the relevant timing diagram.
The Retransmit (RT) input is used in conjunction with the MARK input.
If IDT Standard mode has been selected, the EF flag will go LOW on the
Subsequent retransmit operations may be performed, each time the read
0
– D
9
).
0
– D
19
), or data inputs for 10-bit wide
17
edge of RCLK that retransmit was initiated. OR will return LOW on the next
rising edge of RCLK, which signifies that retransmit setup is complete. Under
FWFT mode, the contents in the marked memory location will be loaded onto
the output register on the next rising edge of RCLK. To access all subsequent
data, a read operation will be required.
pointer returning to the “marked” location. See Figure 24, Retransmit from
Mark (FWFT Mode) for the relevant timing diagram.
MARK
edge of RCLK while MARK is HIGH will mark the memory location of the data
currently present on the output register, in addition placing the device in
retransmit mode. Note, there must be a minimum of 1280 bits (or 160 bytes) of
data between the write pointer and mark location. That is, 20 bits x64 for the
x20 mode and 10 bits x128 for the x10 mode. Also, once the MARK is set, the
write pointer will not increment past the “marked” location until the MARK is
deasserted. This prevents “overwriting” of retransmit data.
mode, a rising edge of RCLK while MARK is LOW will take the device out of
retransmit mode and into normal mode. Any number of MARK locations can
be set during FIFO operation, only the last marked location taking effect. Once
a mark location has been set the write pointer cannot be incremented past this
marked location. During retransmit mode write operations to the device may
continue without hindrance.
FIRST WORD FALL THROUGH (FWFT)
device will operate in IDT Standard mode or First Word Fall Through (FWFT)
mode.
be selected. This mode uses the Empty Flag (EF) to indicate whether or not
there are any words present in the FIFO memory. It also uses the Full Flag
function (FF) to indicate whether or not the FIFO memory has any free space
for writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (REN) and RCLK.
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the outputs (Qn) to be read. It also uses Input Ready (IR) to
indicate whether or not the FIFO memory has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes directly to Qn after
three RCLK rising edges, bringing REN LOW is not necessary. Subsequent
words must be accessed using the Read Enable (REN) and RCLK. Note that
FWFT mode can only be used when the device is configured to Single Data
Rate (SDR) mode.
WRITE CLOCK (WCLK)
If the Write Single Data Rate (WSDR) pin is selected, data will be written only
on the rising edge of WCLK, provided that WEN and WCS are LOW. If the
WSDR is not selected, data will be written on both the rising and falling edge of
WCLK, provided that WEN and WCS are LOW. Data setup and hold times
must be met with respect to the LOW-to-HIGH transition of the WCLK. It is
permissible to stop the WCLK. Note that while WCLK is idle, the FF, IR, and
If FWFT mode has been selected, the OR flag will go HIGH on the rising
Subsequent retransmit operations may be performed, each time the read
The MARK input is used to select Retransmit mode of operation. On a rising
The MARK input must remain HIGH during the whole period of retransmit
During Master Reset, the state of the FWFT input determines whether the
If, at the time of Master Reset, FWFT is LOW, then IDT Standard mode will
If, at the time of Master Reset, FWFT is HIGH, then FWFT mode will be
A write cycle is initiated on the rising and/or falling edge of the WCLK input.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009