RM5261-200-QI PMC-Sierra Inc, RM5261-200-QI Datasheet - Page 20

• Manufacturer Part Number: RM5261-200-QI
• Description: RM5261 Microprocessor with 64-Bit System Bus Data Sheet Released
• Manufacturer: PMC-Sierra Inc

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002241, Issue 1
3. Write-through with write allocate
4. Write-through without write allocate
The most commonly used write policy is write-back, where a store to a cache line does not
immediately cause the main memory to be updated. This increases system performance by
reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish
before issuing a subsequent memory operation. Software can, however, select write-through on a
per-page basis when appropriate, such as for frame buffers.
Associated with the data cache is the store buffer. When the RM5261 executes a store instruction,
this single-entry buffer gets written with the store data while the tag comparison is performed. If
the tag matches, then the data is written into the data cache in the next cycle that the data cache is
not accessed (the next non-load cycle). The store buffer allows the RM5261 to execute a store
every processor cycle and to perform back-to-back stores without penalty. In the event of a store
immediately followed by a load to the same address, a combined merge and cache write occurs
such that no penalty is incurred. The RM5261 cache attributes for both the instruction and data
caches are summarized in Table 3.
Table 3 Cache Attributes
Characteristics
Size
Organization
Line size
Index
Tag
Write policy
Read order
Write order
miss restart after transfer of
Parity
Cache locking
Loads and instruction fetches first search the cache, reading main memory only if the desired
data is not cache resident. On data store operations, the cache is first searched to determine if
the target address is cache resident. If it is resident, the cache contents are updated and main
memory is written, leaving the write-back bit of the cache line unchanged. If the cache lookup
misses, the target line is first brought into the cache and then the write is performed as above.
Loads and instruction fetches first search the cache, reading main memory only if the desired
data is not cache resident. On data store operations, the cache is first searched to determine if
the target address is cache resident. If it is resident, the cache contents are updated and main
memory is written, leaving the write-back bit of the cache line unchanged. If the cache lookup
misses, then only main memory is written.
Instruction
32KB
32B
vAddr
pAddr
n.a.
sub-block
entire line
per-word
set A
2-way set associative
sequential
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
11..0
31..12
Data
32KB
2-way set associative
32B
vAddr
pAddr
write-back/write-through
sub-block
sequential
first double
per-byte
set A
11..0
31..12
Released
20