RM5261-200-QI PMC-Sierra Inc, RM5261-200-QI Datasheet - Page 34

• Manufacturer Part Number: RM5261-200-QI
• Description: RM5261 Microprocessor with 64-Bit System Bus Data Sheet Released
• Manufacturer: PMC-Sierra Inc

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002241, Issue 1
9.3
9.4
System Interface Parameters
Boot-Time Interface Parameters
Parameter
Data Output
Data Setup
Data Hold
Notes
1.
2.
3.
4.
5.
Parameter
Mode Data Setup
Mode Data Hold
Timings are measured from 1.5 V of the clock to 1.5 V of the signal.
Capacitive load for all maximum output timings is 50 pF. Minimum output timings are for a
theoretical no load condition - untested.
Data Output timing applies to all signal pins whether tristate I/O or output only.
Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
Only mode 14:13 = 00 is tested and guaranteed.
4
4
2,3
Symbol
t
t
t
DO
DS
DH
Symbol
t
t
DS
DH
(M)
(M)
Conditions
mode14:13 = 10
mode14:13 = 11
mode14:13 = 00
mode14:13 = 01
t
t
rise
fall
= see above table
= see above table
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
Min
4
0
1
5
5
5
5
(fastest)
(slowest)
Max
200–266 MHz
Min
1.0
1.0
1.0
1.0
2.5
1.0
Units
SysClock cycles
SysClock cycles
Max
4.5
5.0
5.5
6.0
Units
ns
ns
ns
ns
ns
ns
Released
34