RM5261-200-QI PMC-Sierra Inc, RM5261-200-QI Datasheet - Page 26

• Manufacturer Part Number: RM5261-200-QI
• Description: RM5261 Microprocessor with 64-Bit System Bus Data Sheet Released
• Manufacturer: PMC-Sierra Inc

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002241, Issue 1
4
Pin Descriptions
The following is a list of interface, interrupt, and miscellaneous pins available on the RM5261.
Table 5 System Interface
ExtRqst*
Release*
RdRdy*
WrRdy*
ValidIn*
ValidOut*
SysAD[63:0]
SysADC[7:0]
SysCmd[8:0]
SysCmdP
Pin Name
Type
Input
Output
Input
Input
Input
Output
Input/Output
Input/Output
Input/Output
Input/Output
Description
External Request
Signals that the system interface is submitting an external request.
Release interface
Signals that the processor is releasing the system interface to slave
state.
Read Ready
Signals that an external agent can now accept a processor read.
Write Ready
Signals that an external agent can now accept a processor write
request.
Signals that an external agent is now driving a valid address or data on
the SysAD bus and a valid command or data identifier on the SysCmd
bus.
Signals that the processor is now driving a valid address or data on the
SysAD bus and a valid command or data identifier on the SysCmd bus.
System Address/Data bus
A 64-bit address and data bus for communication between the
processor and an external agent.
An 8-bit bus containing parity check bits for the SysAD bus during data
cycles.
A 9-bit bus for command and data identifier transmission between the
processor and an external agent.
For the RM5261, unused on input and zero on output.
Valid Input
Valid Output
System Address/Data check bus
System Command/Data identifier bus
Reserved for system command/data identifier bus parity
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
Released
26