SC16C850V NXP Semiconductors, SC16C850V Datasheet
SC16C850V
Related parts for SC16C850V
SC16C850V Summary of contents
Page 1
... Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates Mbit/s. SC16C850V can be programmed to operate in extended mode where additional advanced UART features are available (see family UART provides enhanced UART functions with 128-byte FIFOs, modem control interface and IrDA encoder/decoder ...
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... Ordering information Table 1. Type number SC16C850VIBS HVQFN32 plastic thermal enhanced very thin quad flat package; SC16C850V_4 Product data sheet www.DataSheet.in Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Supports IrDA version 1.0 (up to 115.2 kbit/s) Standard modem interface or infrared IrDA encoder/decoder interface ...
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... NXP Semiconductors 4. Block diagram AD0 to AD7 IOR IOW RESET LLA CS LOWPWR INT Fig 1. Block diagram of SC16C850V SC16C850V_4 Product data sheet www.DataSheet.in Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface SC16C850V DATA BUS AND CONTROL LOGIC REGISTER SELECT LOGIC ...
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... UART. Status can be tested by reading MSR[5]. Data Terminal Ready (active LOW). A logic 0 on this pin indicates that the SC16C850V is powered-on and ready. This pin can be controlled via the Modem Control Register. Writing a logic 1 to MCR[0] will set the DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. Rev. 04 — ...
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... MCR[3] is set to a logic 1. See Read strobe (active LOW). A HIGH to LOW transition on this signal starts the read cycle. The SC16C850V reads a byte from the internal register and puts the byte on the data bus for the host to retrieve. Write strobe (active LOW). A HIGH to LOW transition on this signal starts the write cycle, and a LOW to HIGH transition transfers the data on the data bus to the internal register ...
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... A low power pin (LOWPWR) is provided to further reduce power consumption by isolating the host interface bus. The SC16C850V is capable of operation Mbit/s with an external 80 MHz clock. With a crystal is capable of operation up to 1.5 Mbit/s. The rich feature set of the SC16C850V is available through internal registers. These features are: selectable and programmable receive and transmit FIFO trigger levels, selectable TX and RX baud rates, and modem interface controls (all standard features) ...
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... The device is in the extended mode when any of these four registers contains any value other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL. 6.3 Internal registers The SC16C850V provides a set of 25 internal registers for monitoring and controlling the functions of the UART. These registers are shown in Table 4. ...
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... Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS logic 1. If CTS transitions from a logic logic 1 indicating a flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C850V will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. ...
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... Following a suspension due to a match of the Xoff characters’ values, the SC16C850V will monitor the receive data stream for a match to the Xon1/Xon2 character value(s match is found, the SC16C850V will resume operation and clear the flags (ISR[4]). ...
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... Interrupt priority and time-out interrupts The interrupts are enabled by IER[7:0]. Care must be taken when handling these interrupts. Following a reset, if Interrupt Enable Register (IER) bit the SC16C850V will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to continuing operations. The ISR indicates the current singular highest priority interrupt only ...
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... The generator divides the input 16 clock by any divisor from SC16C850V divides the basic external clock by 16. The baud rate is configured via the CLKPRES, DLL and DLM internal register functions. Customized baud rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator ...
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... Rev. 04 — 14 January 2008 SC16C850V XTAL1 XTAL2 1 1.8432 MHz 002aaa870 XTAL2 002aac630 DLM DLL program value program value (hexadecimal) (hexadecimal ...
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... SC16C850V_4 Product data sheet www.DataSheet.in Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Figure 6). MCR[3:0] register bits are used for controlling loopback diagnostic testing. Rev. 04 — 14 January 2008 SC16C850V © NXP B.V. 2008. All rights reserved ...
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... FIFO REGISTER FLOW REGISTER CONTROL SELECT LOGIC LOGIC POWER DOWN CONTROL CLOCK AND INTERRUPT BAUD RATE CONTROL GENERATOR LOGIC XTAL1 Rev. 04 — 14 January 2008 SC16C850V TRANSMIT SHIFT REGISTER IR ENCODER MCR[ RECEIVE SHIFT REGISTER IR DECODER MODEM CONTROL LOGIC OP1 OP2 002aac558 XTAL2 © ...
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... Low power feature A low power feature is provided by the SC16C850V to prevent the switching of the host data bus from influencing the sleep current. When the pin LOWPWR is activated (logic HIGH), the device immediately and unconditionally goes into Low Power mode. All clocks are stopped and most host interface pins are isolated to reduce power consumption ...
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... ID address, the controller take no further action, the receiver will receive the subsequent data. SC16C850V_4 Product data sheet www.DataSheet.in Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Rev. 04 — 14 January 2008 SC16C850V © NXP B.V. 2008. All rights reserved ...
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... SC16C850V_4 Product data sheet www.DataSheet.in Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface details the assigned bit functions for the SC16C850V internal registers. The Rev. 04 — 14 January 2008 SC16C850V Section 7.1 through Section 7 ...
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... Table 7. SC16C850V internal registers [ Register Default Bit 7 [2] General Register Set RHR XX bit THR ...
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... Table 7. SC16C850V internal registers …continued [ Register Default Bit 7 [6] Enhanced Register Set EFR 00 Auto CTS ...
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... CTS pin transitions from a logic logic 1. IER[6] RTS interrupt. logic 0 = disable the RTS interrupt (normal default condition) logic 1 = enable the RTS interrupt. The SC16C850V issues an interrupt when the RTS pin transitions from a logic logic 1. IER[5] Xoff interrupt. logic 0 = disable the software flow control, receive Xoff interrupt (normal ...
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... IER versus receive/transmit FIFO polled mode operation When FCR[0] = logic 1, setting IER[3:0] = zeroes puts the SC16C850V in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for TX and/or RX data status. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s) ...
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... Transmit trigger level in 32-byte FIFO mode. These bits are used to set the trigger level for the transmit FIFO interrupt and flow control. The SC16C850V will issue a transmit empty interrupt when the number of characters in FIFO drops below the selected trigger level. Refer to Table 11 ...
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... Interrupt Status Register (ISR) The SC16C850V provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... LCR[2] stop bit length Word length (bits) Stop bit length (bit times Rev. 04 — 14 January 2008 SC16C850V …continued Table 15). Table 16). © NXP B.V. 2008. All rights reserved ...
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... Loopback. Enable the local Loopback mode (diagnostics). In this mode the transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI are disconnected from the SC16C850V I/O pins. Internally the modem data and control pins are connected into a loopback data configuration (see this mode, the receiver and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts’ ...
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... NXP Semiconductors Table 19. MCR[ 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C850V and the CPU. Table 20. Bit SC16C850V_4 Product data sheet www.DataSheet.in Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface ...
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... A modem Status Interrupt will be generated. [1] MSR[2] RI logic change (normal default condition) logic 1 = the RI input to the SC16C850V has changed from a logic logic 1. A modem Status Interrupt will be generated. [1] MSR[1] DSR logic DSR change (normal default condition) logic 1 = the DSR input to the SC16C850V has changed state since the last time it was read ...
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... Remark: EFCR[2:1] has higher priority than EFCR[0]. TXLVLCNT and RXLVLCNT can only be accessed if EFCR[2:1] are zeroes. 7.10 Scratchpad Register (SPR) The SC16C850V provides a temporary data register to store 8 bits of user information. 7.11 Division Latch (DLL and DLM) These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLM stores the most signifi ...
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... Special Character Detect. logic 0 = special character detect disabled (normal default condition) logic 1 = special character detect enabled. The SC16C850V compares each incoming receive character with Xoff2 data match exists, the received data will be transferred to FIFO and ISR[4] will be set to indicate detection of special character. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. When this feature is enabled, the normal software fl ...
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... This register stores the programmable receive interrupt trigger levels for 128-byte FIFO mode. 0x00 = trigger level is set to 1 0x01 = trigger level is set to 1 ... 0x80 = trigger level is set to 128 Rev. 04 — 14 January 2008 SC16C850V [1] [1] (FCR)”. [1] © NXP B.V. 2008. All rights reserved ...
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... For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register Clock prescaler register description Symbol Description CLKPRES[7:4] reserved CLKPRES[3:0] clock prescaler value; reset to 0 Rev. 04 — 14 January 2008 SC16C850V (FCR)”. Table 27 shows transmission control [1] (FCR)”. Table 28 shows transmission control [1] (FCR)”. ...
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... FIFO fall below the trigger level, or becomes empty and the last stop bit has been shift out the transmit shift register. It takes 4 XTAL1 clocks to reset the device. Rev. 04 — 14 January 2008 SC16C850V [1] © NXP B.V. 2008. All rights reserved ...
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... AFCR2[1] RXDisable. Disable receiver. logic 0 = receiver is enabled logic 1 = receiver is disabled AFCR2[0] 9-bitMode. Enable 9-bit mode or Multidrop (RS-485) mode. logic 0 = normal RS-232 mode logic 1 = enable 9-bit mode Rev. 04 — 14 January 2008 SC16C850V © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors 7.23 SC16C850V external reset condition and software reset These two reset methods are identical and will reset the internal registers as indicated in Table Table 33. Register IER FCR ISR LCR MCR LSR MSR EFCR SPR DLL DLM TXLVLCNT RXLVLCNT EFR Xon1 Xon2 ...
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... Except XTAL2. Sleep current might be higher if there is any activity on the UART data bus during Sleep mode. Activate by LOWPWR pin. Rev. 04 — 14 January 2008 SC16C850V Conditions Min Max - 2.5 [ ...
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... Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface = 1. 1.95 V; unless otherwise specified. DD Conditions 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load Rev. 04 — 14 January 2008 SC16C850V Min Typ Max Unit [ MHz ...
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... Rev. 04 — 14 January 2008 SC16C850V data t h(IOWH-D) su(D-IOWH w(IOW) d(IOW) 002aac354 data t dis(IOR-QZ) t d(IOR) t w(IOR) 002aac355 © NXP B.V. 2008. All rights reserved ...
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... Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface active t d(IOW-Q) change of state change of state change of state t d(modem-INT) active active w(clk) Rev. 04 — 14 January 2008 SC16C850V change of state t d(modem-INT) active active t d(IOR-INTL) active active t d(modem-INT) change of state 002aac559 002aac357 © NXP B.V. 2008. All rights reserved ...
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... data bits 6 data bits 7 data bits active transmitter ready t d(start-INT) t d(IOW-TX) active 16 baud rate clock Rev. 04 — 14 January 2008 SC16C850V next data parity stop start bit bit bit d(stop-INT) active t d(IOR-INTL) active 002aac560 ...
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... Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface start TX data IrDA TX data bit time IrDA RX data bit time RX data start Rev. 04 — 14 January 2008 SC16C850V UART frame data bits bit time clock delay ...
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... 2.5 scale (1) ( 5.1 3.25 5.1 3.25 0.2 0.5 3.5 4.9 2.95 4.9 2.95 REFERENCES IEC JEDEC JEITA - - - MO-220 - - - Rev. 04 — 14 January 2008 SC16C850V detail 0.5 3.5 0.1 0.05 0.05 0.1 0.3 EUROPEAN ISSUE DATE PROJECTION © NXP B.V. 2008. All rights reserved. SOT617-1 c ...
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... Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities Rev. 04 — 14 January 2008 SC16C850V © NXP B.V. 2008. All rights reserved ...
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... Package reflow temperature ( C) Volume (mm < 350 235 2.5 220 Lead-free process (from J-STD-020C) Package reflow temperature ( C) Volume (mm < 350 260 260 250 Figure 16. Rev. 04 — 14 January 2008 SC16C850V Figure 16) than a SnPb process, thus 3 ) 350 220 220 3 ) 350 to 2000 > 2000 260 260 250 245 ...
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... Infrared Data Association Integrated Service Digital Network Least Significant Bit Most Significant Bit Printed-Circuit Board Restriction of Hazardous Substances directive Universal Asynchronous Receiver/Transmitter Variable Latency Input/Output Rev. 04 — 14 January 2008 SC16C850V peak temperature time 001aac844 © NXP B.V. 2008. All rights reserved ...
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... Document ID Release date SC16C850V_4 20080114 • Modifications: Table 7 “SC16C850V internal – R/W value for register TXLVLCNT changed from “R/W” to “R” – R/W value for register RXLVLCNT changed from “R/W” to “R” • Table 37 “Dynamic – changed symbol/parameter from “f – ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 04 — 14 January 2008 SC16C850V © NXP B.V. 2008. All rights reserved ...
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... Flow Control Trigger Level Low (FLWCNTL 7.19 Clock prescaler (CLKPRES 7.20 RS-485 turn-around time delay (RS485TIME) 32 7.21 Advanced Feature Control Register 1 (AFCR1 7.22 Advanced Feature Control Register 2 (AFCR2 7.23 SC16C850V external reset condition and software reset Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 35 9 Static characteristics . . . . . . . . . . . . . . . . . . . 35 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 36 10.1 Timing diagrams Package outline . . . . . . . . . . . . . . . . . . . . . . . . 41 12 Soldering of SMD packages ...