SC16C850V NXP Semiconductors, SC16C850V Datasheet - Page 16

• Manufacturer Part Number: SC16C850V
• Description: XScale VLIO bus interface
• Manufacturer: NXP Semiconductors

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SC16C850V_4
Product data sheet
6.13.3.1 Normal Multi-drop mode
6.13.1 Auto RS-485 RTS control
6.13.2 RS-485 RTS inversion
6.13.3 Auto 9-bit mode (RS-485)
6.13 RS-485 Features
Normally the RTS pin is controlled by MCR bit 1, or if hardware flow control is enabled, the
logic state of the RTS pin is controlled by the hardware flow control circuitry. EFCR2
register bit 4 will take the precedence over the other two modes; once this bit is set, the
transmitter will control the state of the RTS pin. The transmitter automatically asserts the
RTS pin (logic 0) once the host writes data to the transmit FIFO, and de-asserts the RTS
pin (logic 1) once the last bit of the data has been transmitted.
To use the auto RS-485 RTS mode, the software would have to disable the hardware flow
control function.
EFCR2 bit 5 reverses the polarity of the RTS pin if the UART is in auto RS-485 RTS mode.
When the transmitter has data to be sent, it will de-assert the RTS pin (logic 1), and when
the last bit of the data has been sent out, the transmitter asserts the RTS pin (logic 0).
EFCR2 bit 0 is used to enable the 9-bit mode (Multi-drop or RS-485 mode). In this mode
of operation, a ‘master’ station transmits an address character followed by data characters
for the addressed ‘slave’ stations. The slave stations examine the received data and
interrupt the controller if the received character is an address character (parity bit = 1).
To use the auto 9-bit mode the software would have to disable the hardware and software
flow control functions.
The 9-bit Mode in EFCR (bit 0) is enabled, but not Special Character Detect (EFR bit 5).
The receiver is set to Force Parity 0 (LCR[5:3] = 111) in order to detect address bytes.
With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an
address byte is received (parity bit = 1). This address byte will cause the UART to set the
parity error. The UART will generate a line status interrupt (IER bit 2 must be set to ‘1’ at
this time), and at the same time puts this address byte in the RX FIFO. After the controller
examines the byte it must make a decision whether or not to enable the receiver; it should
enable the receiver if the address byte addresses its ID address, and must not enable the
receiver if the address byte does not address its ID address.
If the controller enables the receiver, the receiver will receive the subsequent data until
being disabled by the controller after the controller has received a complete message from
the ‘master’ station. If the controller does not disable the receiver after receiving a
message from the ‘master’ station, the receiver will generate a parity error upon receiving
another address byte. The controller then determines if the address byte addresses its ID
address, if it is not, the controller then can disable the receiver. If the address byte
addresses the ‘slave’ ID address, the controller take no further action, the receiver will
receive the subsequent data.
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Rev. 04 — 14 January 2008
SC16C850V
© NXP B.V. 2008. All rights reserved.
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