MBM29BS12DH Fujitsu Media Devices, MBM29BS12DH Datasheet
MBM29BS12DH
Related parts for MBM29BS12DH
MBM29BS12DH Summary of contents
Page 1
... Max Burst Access Time (ns) Max OE Access Time (ns) Max Address Access Time (ns) Asynchronous Max CE Access Time (ns) Max OE Access Time (ns) PACKAGE 16) BIT 15 supply. 12 and 5 MBM29BS12DH Non-Handshaking 80-ball plastic FBGA (BGA-80P-M04) DS05-20910-2E are not required for write or erase CC (Continued) MBM29FS12DH Handshaking ...
Page 2
MBM29BS/FS12DH (Continued) The device provides truly high performance non-volatile memory solution. The device offers fast burst access frequency of 66 MHz with initial access times Handshaking mode, allowing operation of high-speed microprocessors without wait states. To ...
Page 3
FEATURES • 0.13 m process technology • Single 1.8 V read, program and erase (1. 1.95 V) • Simultaneous Read/Write operation (Dual Bank) • FlexBank Bank A: 16 Mbit (4 Kwords 8 and 32 Kwords ...
Page 4
MBM29BS/FS12DH (Continued) • Sector Protection Persistent sector protection Password sector protection ACC protects all sectors WP protects the outermost words on both ends of boot sectors, regardless of sector protection / unprotection status. • Handshaking feature ...
Page 5
PIN ASSIGNMENT N.C. N.C. N. N.C. N. RESET C4 D4 RDY ACC ...
Page 6
MBM29BS/FS12DH BLOCK DIAGRAM CCQ V SSQ Bank A address RESET State WE Control CE & OE Command WP Register AVD CLK ACC Bank D address LOGIC SYMBOL 6 15 Cell ...
Page 7
DEVICE BUS OPERATION MBM29BS/FS12DH User Bus Operations Table Operation Asynchronous Mode Operations (Default) Asynchronous Read Addresses Latched * 1 Standby Output Disable Write - WE address latched * 3 Write - AVD address latched * 3 Boot Block Sector Write ...
Page 8
MBM29BS/FS12DH MBM29BS/FS12DH Command Definitions Table First Bus Bus Write Command Write Cycle Cycles Sequence Req’d Addr. Data Addr. Read / Reset 1 XXXh F0h Read / Reset 3 555h AAh 2AAh Autoselect 3 555h AAh 2AAh Program 4 555h AAh ...
Page 9
First Bus Bus Write Command Write Cycle Cycles Sequence Req’d Addr. Data Password Verify 4 555h AAh 2AAh 55h Password Mode Locking Bit 6 555h AAh 2AAh 55h Program Persistent Protection Mode 6 555h AAh 2AAh 55h Locking Bit ...
Page 10
MBM29BS/FS12DH (Continued) *1: This command is valid during Fast Mode. *2: This command is valid during HiddenROM mode. *3: The data “00h” is also acceptable. Notes : Address bits “H” or “L” for all ...
Page 11
FLEXIBLE SECTOR-ERASE ARCHITECTURE Bank Sector Bank Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 0 0 ...
Page 12
MBM29BS/FS12DH Bank Address Bank Sector SA39 0 0 SA40 0 0 SA41 0 0 SA42 0 0 SA43 0 0 SA44 0 0 SA45 0 0 SA46 0 0 SA47 0 0 SA48 0 0 SA49 ...
Page 13
Bank Address Bank Sector SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 0 ...
Page 14
MBM29BS/FS12DH (Continued) Bank Address Bank Sector SA117 0 1 SA118 0 1 SA119 0 1 SA120 0 1 SA121 0 1 SA122 0 1 SA123 0 1 SA124 0 1 SA125 0 1 Bank B SA126 ...
Page 15
Bank Sector Bank Address SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 1 ...
Page 16
MBM29BS/FS12DH Bank Sector Bank Address SA174 1 0 SA175 1 0 SA176 1 0 SA177 1 0 SA178 1 0 SA179 1 0 SA180 1 0 SA181 1 0 SA182 1 0 SA183 1 0 SA184 ...
Page 17
Bank Address Bank Sector SA213 1 1 SA214 1 1 SA215 1 1 SA216 1 1 SA217 1 1 SA218 1 1 SA219 1 1 SA220 1 1 SA221 1 1 Bank C SA222 ...
Page 18
MBM29BS/FS12DH Bank Sector Bank Address SA231 1 1 SA232 1 1 SA233 1 1 SA234 1 1 SA235 1 1 SA236 1 1 SA237 1 1 SA238 1 1 SA239 1 1 SA240 1 1 SA241 ...
Page 19
Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 ...
Page 20
MBM29BS/FS12DH Sector Group SGA28 0 1 SGA29 0 1 SGA30 0 1 SGA31 0 1 SGA32 0 1 SGA33 0 1 SGA34 0 1 SGA35 0 1 SGA36 0 1 SGA37 0 1 SGA38 0 ...
Page 21
Sector Group SGA52 SGA53 SGA54 SGA55 SGA56 SGA57 SGA58 SGA59 1 1 ...
Page 22
MBM29BS/FS12DH Common Flash Memory Interface Code Table Description A Query-unique ASCII string “QRY” Primary OEM Command Set 2h: AMD/FJ standard type Address for Primary Extended Table Alternate OEM Command Set (00h = not applicable) Address for Alternate OEM Extended Table ...
Page 23
FUNCTIONAL DESCRIPTION Asynchronous Read Operation (Non-Burst) Mode When the device first powers up enabled for asynchronous read operation. CLK is ignored in this operation. To read data from the memory array, the system must first assert a valid ...
Page 24
MBM29BS/FS12DH Configuration Register The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. Burst Suspend / Resume The Burst Suspend / Resume ...
Page 25
Bank 1 Bank Splits Volume Combination 1 16 Mbit Bank Mbit Bank Mbit Bank Mbit Bank D Example of Virtual Banks Combination Table Bank 1 Bank Combination of Splits Megabits Memory ...
Page 26
MBM29BS/FS12DH Standby Mode There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and the other via the RESET pin only. When using both pins, a CMOS standby mode is ...
Page 27
At Synchronous Mode When the Configuration Register is set to Synchronous mode, the device has the capability of performing two types of programming operation. WE latch - The system must drive CE, WE, and AVD to V Addresses are ...
Page 28
MBM29BS/FS12DH HiddenROM area is devided into two regions, which are Factory Locked area and Customer Locked area. The Factory Locked area is 64 words (address: 000000h - 00003Fh) that is programmed and locked at Fujitsu. The Customer Locked area is ...
Page 29
This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are ...
Page 30
MBM29BS/FS12DH –DPB Status The programming of the DPB for a given sector can be verified by writing a DPB status verify command to the device. –PPB Status The programming of the PPB for a given sector can be verified by ...
Page 31
Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the password. Fujitsu recommends that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the particular ...
Page 32
MBM29BS/FS12DH COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Some commands require Bank Address (BA) input. When command sequences are input into a bank reading, the commands have priority over the ...
Page 33
Handshaking Option If the device is equipped with the handshaking option, the host system should set address bits (A (0, 1, 0)for a clock frequency of 54/66 MHz for the system/device to execute at maximum speed. The device will ...
Page 34
MBM29BS/FS12DH RDY Configuration Setting The device can be set so that RDY goes active either with valid data or one data cycle before active data. Address bit A determines this setting; "1" for RDY active with data, "0" for RDY ...
Page 35
FS12DH User Bus Operations Table” in “ DEVICE BUS OPERATIION”. ) The manufacture and device codes can be read from the selected bank. To read ...
Page 36
MBM29BS/FS12DH Sector Erase Command Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. After ...
Page 37
Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ After entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand ...
Page 38
MBM29BS/FS12DH HiddenROM Program Command To program the data to the HiddenROM area, write the HiddenROM program command sequence during HiddenROM mode. This command is the same as the program command in usual except to write the command during HiddenROM mode. ...
Page 39
Mode Locking Bit is programmed. If not, then the user needs to repeat this program sequence from the 4th cycle of "SPML/68h". Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the HiddenROM Exit command. PPB ...
Page 40
MBM29BS/FS12DH PPB Program Command The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (A as the program command 60h. ...
Page 41
Status Embedded Program Algorithm Embedded Erase Sector Erase Non-Erase Sector Algorithm Erase Suspend Read In Progress (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Embedded Erase Algorithm ...
Page 42
MBM29BS/FS12DH DQ 6 Toggle Bit I The device also features the “Toggle Bit I” method to indicate to the host system that the Embedded Algorithms are in progress or completed. During Embedded Program or Erase Algorithm cycle, successive ...
Page 43
DQ 2 Toggle Bit II This toggle bit II, along with DQ 6 Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will ...
Page 44
MBM29BS/FS12DH Data Protection The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up device automatically resets internal state machine to Read mode. Also, ...
Page 45
ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All inputs and I/Os pins except as noted below Power Supply Voltage* 1 I/O’s Power Supply Voltage 1, 3 ACC* * ...
Page 46
MBM29BS/FS12DH MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT +0.8 V –0.5 V –2.0 V Figure +1.0 V Figure Maximum Undershoot Waveform ...
Page 47
DC CHARACTERISTICS • CMOS Compatible Parameter Symbol Input Leakage Current Output Leakage Current I V Active Burst Read CC I CCB Current V Active Asynchronous CC I CC1 Read Current Active Current CC2 V Current ...
Page 48
MBM29BS/FS12DH AC CHARACTERISTICS • Synchronous/Burst Read Parameter Latency (Even Address in Handshake Mode) Latency—(Non-Handshake or Odd Address in Handshake mode) Burst Access Time Valid Clock to Output Delay Address Setup Time to CLK* Address Hold Time from CLK* Data Hold ...
Page 49
Asynchronous Read Parameter Read Cycle Time Access Time from CE Low Asynchronous Access Time* Output Enable to Output Valid Output Read Enable Hold Toggle and Data Polling Time Chip Enable to High-Z CE High During Toggle Bit Polling Output ...
Page 50
MBM29BS/FS12DH • Write (Erase/Program) Operations Parameter Write Cycle Time Address Setup Time Address Hold Time AVD Low Time CE Low to AVD High Data Setup Time Data Hold Time Read Recovery Time Before Write CE Hold Time Write Pulse Width ...
Page 51
ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Word Programming Time Chip Programming Time Erase/Program Cycle 100,000 Note : Test conditions T = 25°C, A Typical Erase conditions T = 25° Typical Program conditions T FBGA PIN CAPACITANCE ...
Page 52
MBM29BS/FS12DH TIMING DIAGRAM • Key to Switching Wavwforms t CES CLK t AVSC AVD t AVHC t ACS ACH High-Z RDY Notes ...
Page 53
CES CE 1 CLK t AVSC AVD t AVHC t ACS ACH High Notes : Figure shows total number of wait states ...
Page 54
MBM29BS/FS12DH 7 cycles for initial access shown. t CES CLK t AVSC AVD t AVHC t ACS ACH OES High-Z RDY ...
Page 55
CES CLK t AVSC AVD t AVHC t ACS ACH IACC t ACC t OES t ...
Page 56
MBM29BS/FS12DH t CES CLK t AVSC AVD t AVHC t ACS ACH High-Z RDY Note : Figure assumes 6 wait states for ...
Page 57
Suspend CLK V IH AVD Address t OES OE t CKZ Data D20 t RACC RDY Note : Figure is for any even address other than 3Eh (or multiple thereof). The Set Configuration Register command sequence must ...
Page 58
MBM29BS/FS12DH Suspend CLK V IH AVD Address t OES OE t CKZ Data D23 t RACC RDY Note : Figure is for any odd address other than 3Fh (or multiple thereof). The Set Configuration Register command sequence ...
Page 59
Suspend CLK AVD A(0) Address OE Data RDY CE Note : Figure assumes 6 wait states for initial access and synchronous read. The starting address is Even. The Set Configuration Register command sequence must be ...
Page 60
MBM29BS/FS12DH CLK AVD A(1) Address OE Data RDY CE Note : Figure assumes 6 wait states for initial access and synchronous read. The starting address is Odd. The Set Configuration Register command sequence must be written ...
Page 61
Suspend CLK V IH AVD Address t OES OE t CKZ Data D20 t RACC RDY Note : The Set Configuration Register command sequence must be written with A18=1; device will output RDY with valid data. The ...
Page 62
MBM29BS/FS12DH CLK AVD A(n) Address OE Data RDY CE Note : Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence must be written with A18=1; device will output RDY ...
Page 63
Suspend CLK AVD A(n) Address OE Data RDY CE Notes : Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence must be written with A18=1; device will ...
Page 64
MBM29BS/FS12DH Address Outputs Notes : AVD is assumed Configuration Register is set to Asynchronous mode Address Stable t ACC OEH t CE High Figure 15 ...
Page 65
CE, OE RESET t RP Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms CE, OE RESET t RP Figure RESET Address Data t RH Figure 17 MBM29BS/FS12DH t ...
Page 66
MBM29BS/FS12DH Program Command Sequence (last two cycles) CLK t AVSW AVD V IL 3rd Bus Cycle 555h Address A0h Data GHWL WE Notes : PA = Program Address, PD ...
Page 67
Program Command Sequence (last two cycles) CLK t CLAH AVD t AVDP t AAH t AAS Address 555h Data A0h AHWL VCS V CC Notes ...
Page 68
MBM29BS/FS12DH Program Command Sequence (last two cycles) CLK t AVSW t AVHW AVD Address 555h Data A0h WLC VCS V CC Notes : PA = ...
Page 69
Program Command Sequence (last two cycles) CLK t ACS t ACH CE t AVSC t AVHC AVD Address 555h Data A0h CAS CWL WPH VCS Vcc ...
Page 70
MBM29BS/FS12DH Program Command Sequence (last two cycles) CLK t AVSW t AVHW AVD Address 2AAh Data 55h t AVSC WLC VCS V CC Notes : ...
Page 71
CE AVD WE Address Data Don't Care ACC t VID Note : Use setup and hold times from conventional program operation. Figure 23 Accelerated Fast mode Programming Timing MBM29BS/FS12DH PA A0h Don't ...
Page 72
MBM29BS/FS12DH AVD OEH WE t ACC Address Notes : Status reads in figure are shown as asynchronous mode Valid Address. Two read cycles are required to determine status. When ...
Page 73
CE CLK AVD Address IACC Data RDY Notes : The timings are similar to synchronous read timings Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the ...
Page 74
MBM29BS/FS12DH Data AVD OE 1 CLK Wait State Decoding Addresses "101" 5 programmed, 7 total "100" 4 programmed, 6 total ...
Page 75
Last Cycle in Program or Sector Erase Command Sequence WPH t DS Data PD/30h Address PA/SA AVD Note : Breakpoints in waveforms indicate that system may alternately read ...
Page 76
MBM29BS/FS12DH Figure Power-up/ Hardware Reset Asynchronous Read Mode Only Set Burst Mode Set Burst Mode Configuration Register Configuration Register Command for Command for Synchronous Mode Asynchronous Mode ( Synchronous Read ...
Page 77
FLOW CHART EMBEDDED ALGORITHM Increment Address Figure 29 MBM29BS/FS12DH Start Write Program Command Sequence (See Below) Data Polling Device No Verify Data ? Yes No Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 555h/AAh 2AAh/55h 555h/A0h Program Address/Program ...
Page 78
MBM29BS/FS12DH EMBEDDED ALGORITHM Chip Erase Command Sequence (Address/Command): 555h/AAh 2AAh/55h 555h/80h 555h/AAh 2AAh/55h 555h/10h Notes : See “MBM29BS/FS12DH Command Definitions” in “ DEVICE BUS OPERATION” for erase command sequence. See the section Start Write Erase Command ...
Page 79
rechecked even “1” because Figure 31 MBM29BS/FS12DH VA = Address for programming = Any of the sector addresses within the sector being erased Start during sector erase or multiple ...
Page 80
MBM29BS/FS12DH Read DQ Read DQ No Read DQ Read DQ Reset Command *1 : Read toggle bit twice to determine whether it is toggling Recheck toggle bit because it may stop toggling Start *1 ...
Page 81
FAST MODE ALGORITHM Increment Address Figure 33 Embedded Programming Algorithm for Fast Mode MBM29BS/FS12DH Start 555h/AAh 2AAh/55h 555h/20h XXXXh/A0h Program Address/Program Data Data Polling Device No Verify Data? Yes No Last Address ? Yes Programming Completed XXXXh/90h XXXXh/F0h 15 Set ...
Page 82
MBM29BS/FS12DH ORDERING INFORMATION Part No. MBM29BS/FS12DH15PBT MBM29BS/FS12 DEVICE NUMBER/DESCRIPTION MBM29BS12 128 Mega-bit (8M 1.8 V-only Read, Write, and Erase with Non-Handshake MBM29FS12 128 Mega-bit (8M 1.8 V-only Read, Write, and Erase with Handshake 82 15 Package Access ...
Page 83
PACKAGE DIMENSIONS 80-ball plastic FBGA (BGA-80P-M04) 11.00±0.10(.433±.004) (.315±.004) (INDEX AREA) 2003 FUJITSU LIMITED B80004S-c-1-1 C MBM29BS/FS12DH +0.12 1.08 –0.13 (Mounting height) +.005 .043 –.005 0.38±0.10 (Stand off) (.015±.004) A 8.00±0.10 0.10(.004 80-ø0.45±0.05 (80-ø.018±.002) Dimensions in mm (inches) Note ...
Page 84
MBM29BS/FS12DH FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in ...