MBM29BS12DH Fujitsu Media Devices, MBM29BS12DH Datasheet - Page 38

• Manufacturer Part Number: MBM29BS12DH
• Description: (MBM29FS12DH / MBM29BS12DH) BURST MODE FLASH MEMORY CMOS 128M (8M X 16) BIT
• Manufacturer: Fujitsu Media Devices

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MBM29BS/FS12DH
HiddenROM Program Command
HiddenROM Protect Command
Password Program Command
Password Verify Command
Password Protection Mode Locking Bit Program Command
Persistent Sector Protection Mode Locking Bit Program Command
To program the data to the HiddenROM area, write the HiddenROM program command sequence during
HiddenROM mode. This command is the same as the program command in usual except to write the command
during HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the
DQ
other than the HiddenROM area is selected to program, data of the address will be changed.
To protect the HiddenROM area, write the HiddenROM Protect command sequence during HiddenROM mode.
After issuing "OPBP/48h" at 4th bus cycle, the device requires approximately 150us time out period for protecting
HiddenROM area. Then by writing "OPBP/48h" at 5th bus cycle, the device outputs verify data at DQ0. If DQ0=1
then HiddenROM area is protected. If not, then the user needs to repeat this program sequence from the 4th
cycle of "OPBP/48h".
The Password Program Command permits programming the password that is used as part of the hardware
protection scheme. The actual password is 64-bits long. 4 Password Program commands are required to program
the password. The user must enter the unlock cycle, password program command (38h) and the program
address/data for each portion of the password when programming. There are no provisions for entering the
2-cycle unlock cycle, the password program command, and all the password data. There is no special addressing
order required for programming the password. Also, when the password is undergoing programming, Simulta-
neous Operation is disabled. Read operations to any memory location will return the programming status. Once
the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification.
The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is
programmed as a “0” results in a time-out by the Embedded Program Algorithm with the cell remaining as a “0”.
The password is all F’s when shipped from the factory. All 64-bit password combinations are valid as a password.
Writing the HiddenROM Exit command returns the device back to normal operation.
The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password
Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts
to verify the Password, the device will always drive all F’s onto the DQ data bus.
Also, the device will not operate in Simultaneous Operation when the Password Verify command is executed.
Only the password is returned regardless of the bank address. The lower two address bits (A
the Password Verify. Writing the HiddenROM Exit command returns the device back to normal operation.
The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking
Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection
Mode Locking Bit cannot be erased and the Persistent Sector Protection Locking Bit program circuitry is disabled,
thereby forcing the device to remain in the Password Protection mode. After issuing "PL/68h" at 4th bus cycle,
the device requires approximately 150µs time out period for programming the Password Protection Mode Locking
Bit. Then by writing "PL/48h" at 5th bus cycle, the device outputs verify data at DQ0. If DQ0=1 then Password
Protection Mode Locking Bit is programmed. If not, then the user needs to repeat this program sequence from
the 4th cycle of "PL/68h". Exiting the Password Protection Mode Locking Bit Program command is accomplished
by writing the HiddenROM Exit command.
The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection
Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. By disabling
the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector
Protection mode of operation, once this bit is set. After issuing "SPML/68h" at 4th bus cycle, the device requires
approximately 150 µs time out period for programming the Persistent Protection Mode Locking Bit. Then by
writing "SPML/48h" at 5th bus cycle, the device outputs verify data at DQ0. If DQ0=1 then Persistent Protection
7
data polling, and DQ
6
toggle bit. Need to pay attention to the address to be programmed. If the address
15
1
:A
0
) are valid during