MBM29BS12DH Fujitsu Media Devices, MBM29BS12DH Datasheet - Page 43

• Manufacturer Part Number: MBM29BS12DH
• Description: (MBM29FS12DH / MBM29BS12DH) BURST MODE FLASH MEMORY CMOS 128M (8M X 16) BIT
• Manufacturer: Fujitsu Media Devices

DQ
Toggle Bit II
Reading Toggle Bits DQ
RDY: Ready
This toggle bit II, along with DQ
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
suspended sector will indicate a logic “1” at the DQ
DQ
Program operation is in progress. The behavior of these two status bits, along with that of DQ
as follows :
For example, DQ
(DQ
Furthermore DQ
if this bit is read from an erasing sector.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
Whenever the system initially begins reading toggle bit status, it must read DQ
to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ
However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ
determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ
went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ
gone high. The system may continue to monitor the toggle bit and DQ
mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the
status of the operation. (Refer to “Toggle Bit Algorithm” in “ FLOW CHART”. )
The RDY is a dedicated output that, when the device is configured in the Synchronous mode, indicates (when
at logic low) the system should wait 1 clock cycle before expecting the next word of data. Using the RDY
Configuration Command Sequence, RDY can be set so that a logic low indicates the system should wait 2 clock
cycles before expecting valid data.
In Synchronous mode RDY functions only data valid indicator. The RDY output to be low during the initial access
in burst mode.
When the device is configured in Asynchronous mode, the RDY is an open-drain output which indicates whether
an Embedded Alogorithm is in progress or completed (RY/BY). If output is low, the device is busy with either a
program or erase operation. If output is high (RY/BY should be pulled up), the device is ready to accept any
read/write or erase operation. If the device is placed in an Erase Suspend mode, RDY output will be High-Z.
During programming at Asynchronous mode, the RDY pin is driven low after the rising edge of the fourth write
pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The
RDY pin will indicate a busy condition during RESET pulse.
Since this is an open-drain output at Asynchronous mode, RDY pins can be tied together in parallel with a pull-
up resistor to V
2
2
6
2
to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase
is different from DQ
toggles while DQ
CCQ
2
2
can also be used to determine which sector is being erased. At the erase mode, DQ
.
and DQ
6
7
6
/DQ
to DQ
does not. ) See also “Hardware Sequence Flags Table”.
2
6
in that DQ
2
can be used together to determine if the erase-suspend-read mode is in progress.
0
on the following read cycle.
6
, can be used to determine whether the device is in the Embedded Erase
6
toggles only when the standard program or Erase, or Erase Suspend
5
is high (see the section on DQ
2
bit.
2
to toggle during the Embedded Erase Algorithm. If the
MBM29BS/FS12DH
5
through successive read cycles, deter-
5
) . If it is, the system should then
7
to DQ
0
at least twice in a row
7
, is summarized
5
2
has not
toggles
15
5
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