cy2sstv16857zxi Fairchild Semiconductor, cy2sstv16857zxi Datasheet - Page 6

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cy2sstv16857zxi

Manufacturer Part Number
cy2sstv16857zxi
Description
14-bit Register With Sstl-2 Compatible I/o And Reset
Manufacturer
Fairchild Semiconductor
Datasheet
www.fairchildsemi.com
C
Capacitance
Note 15: T
AC Loading and Waveforms
Note: C
Note: I
FIGURE 5. Voltage Waveforms - Setup and Hold Times
IN
Symbol
FIGURE 3. Voltage and Current Waveforms Inputs
and I
DD
L
includes probe and jog capacitance
tested with clock and data inputs held at V
A
O
Data Pin Input Capacitance
CK, CK - Input Capacitance
RESET

0 mA.
25
FIGURE 7. Voltage Waveforms -
RESET Removal Delay Times
q
C, f
FIGURE 1. AC Test Circuit
Active and Inactive Times
1 MHz, Capacitance is characterized but not tested.
Parameter
(Note 15)
DD
or GND,
Min
2.0
2.5
2.5
(See Notes A through F below)
Typ
6
Note A: All input pulses are supplied by generators having
the following characteristics:
Note B: The outputs are measured one at a time with one
transition per measurement.
Note C: V
Note D: V
ential inputs. V
Note E: V
ential inputs. V
Note F: Removal time (t
held active HIGH. The propagation time from CK to the cor-
responding output must meet valid timing specifications for
the measurement to be accurate.
PRR
(unless otherwise specified).
FIGURE 2. Voltage Waveforms - Pulse Duration
Max
3.0
3.5
3.5
d
10 MHz, Z
TT
IH
IL
RESET Propagation Delay Times
FIGURE 4. Voltage Waveforms -
FIGURE 6. Voltage Waveforms -
V
V
IH
IL
V
Units
REF
Propagation Delay Times
REF
REF
pF
pF
pF
GND for LVCMOS input.
V
0


DD
310 mV (AC voltage levels) for differ-
310 mV (AC voltage levels) for differ-
V
50
V
V
V
for LVCMOS input.
DD
REM
DD
DD
DD
:
/2.
, input slew rate
) is tested with one data input
2.5V, V
2.5V, V
2.5V, V
I
ICR
I
Conditions
V
V
REF
DD
1.25V, V
to GND
r
350 mV
1V/ns
I(PP)
r
360 mV
20%

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