a1240a-pg132b Actel Corporation, a1240a-pg132b Datasheet - Page 33

• Manufacturer Part Number: a1240a-pg132b
• Description: Hirel Fpgas
• Manufacturer: Actel Corporation

A 12 80 X L T i m i n g C h ar a c t er i st i c s
(W or st -C as e M il it ar y Cond it ion s, V
Parameter
Logic Module Propagation Delays
t
t
t
t
Logic Module Predicted Routing Delays
t
t
t
t
t
Logic Module Sequential Timing
t
t
t
t
t
t
t
t
t
t
t
f
Notes:
1.
2.
3.
4.
PD1
CO
GO
RS
RD1
RD2
RD3
RD4
RD8
SUD
HD
SUENA
HENA
WCLKA
WASYN
A
INH
INSU
OUTH
OUTSU
MAX
For dual-module macros, use t
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained
from the DirectTime Analyzer utility.
Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
Description
Single Module
Sequential Clk to Q
Latch G to Q
Flip-Flop (Latch) Reset to Q
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Flip-Flop (Latch) Data Input Setup
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active Pulse
Width
Flip-Flop (Latch) Asynchronous Pulse
Width
Flip-Flop Clock Input Period
Input Buffer Latch Hold
Input Buffer Latch Setup
Output Buffer Latch Hold
Output Buffer Latch Setup
Flip-Flop (Latch) Clock Frequency
PD1
+ t
3, 4
1
RD1
+ t
2
PDn
C C
, t
CO
= 4.5 V, T
+ t
RD1
+ t
PDn
J
, or t
= 1 25° C)
PD1
Min.
10.7
0.4
0.0
1.1
0.0
5.3
5.3
0.0
0.4
0.0
0.4
+ t
‘–1’ Speed
RD1
+ t
SUD
Max.
3.7
3.7
3.7
3.7
1.7
2.5
3.1
3.7
7.0
90
, whichever is appropriate.
Min.
12.3
0.5
0.0
1.2
0.0
6.1
6.1
0.0
0.4
0.0
0.4
‘Std’ Speed
Max.
4.3
4.3
4.3
4.3
2.1
3.0
3.6
4.3
8.3
75
H iR e l F PG A s
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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