74LCX374BQX Fairchild Semiconductor, 74LCX374BQX Datasheet

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74LCX374BQX

Manufacturer Part Number
74LCX374BQX
Description
IC FLIP FLOP OCT D LV 20-DQFN
Manufacturer
Fairchild Semiconductor
Series
74LCXr
Type
D-Type Busr
Datasheet

Specifications of 74LCX374BQX

Function
Standard
Output Type
Tri-State Non Inverted
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
150MHz
Delay Time - Propagation
8.5ns
Trigger Type
Positive Edge
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-WQFN Exposed Pad, 20-DQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LCX374BQX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
©2006 Fairchild Semiconductor Corporation
74LCX374 Rev. 1.6.0
74LCX374
Low Voltage Octal D-Type Flip-Flop
with 5V Tolerant Inputs and Outputs
Features
Note:
1. To ensure the high impedance state during power up
Ordering Information
Note:
2. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
74LCX374WM
74LCX374SJ
74LCX374BQX
74LCX374MSA
74LCX374MTC
5V tolerant inputs and outputs
2.3V–3.6V V
8.5ns t
Power-down high impedance inputs and outputs
Supports live insertion/withdrawal
±24mA output drive (V
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds JEDEC 78 conditions
ESD performance
– Human Body Model
– Machine Model
Leadless DQFN package
or down, OE should be tied to V
resistor: the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
Order Number
All packages are lead free per JEDEC: J-STD-020B standard.
PD
max (V
CC
(2)
specifications provided
CC
200V
3.3V), 10µA I
CC
2000V
Package
Number
MLP20B
MSA20
MTC20
M20D
M20B
3.0V)
CC
(1)
CC
through a pull-up
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),
JEDEC MO-241, 2.5 x 4.5mm
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm
Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
max
General Description
The LCX374 consists of eight D-type flip-flops featuring
separate D-type inputs for each flip-flop and 3-STATE
outputs for bus-oriented applications. A buffered clock
(CP) and Output Enable (OE) are common to all flip-
flops. The LCX374 is designed for low voltage appli-
cations with capability of interfacing to a 5V signal
environment.
The LCX374 is fabricated with an advanced CMOS
technology to achieve high speed operation while main-
taining CMOS low power dissipation.
Package Description
February 2008
www.fairchildsemi.com

Related parts for 74LCX374BQX

74LCX374BQX Summary of contents

Page 1

... Ordering Information Package Order Number Number 74LCX374WM M20B 74LCX374SJ M20D (2) 74LCX374BQX MLP20B 74LCX374MSA MSA20 74LCX374MTC MTC20 Note: 2. DQFN package available in Tape and Reel only. Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ...

Page 2

... Pad Assignments for DQFN GND CP (Top View) Pin Description Pin Names D –D Data Inputs Clock Pulse Input OE Output Enable Input O –O 3-STATE Outputs 0 7 ©2006 Fairchild Semiconductor Corporation 74LCX374 Rev. 1.6.0 Logic Symbol Truth Table HIGH Voltage Level LOW Voltage Level Immaterial ...

Page 3

... Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©2006 Fairchild Semiconductor Corporation 74LCX374 Rev. 1.6 www.fairchildsemi.com ...

Page 4

... OL T Free-Air Operating Temperature Input Edge Rate Notes Absolute Maximum Rating must be observed Unused inputs must be held HIGH or LOW. They may not float. ©2006 Fairchild Semiconductor Corporation 74LCX374 Rev. 1.6.0 Conditions Output in 3-STATE (3) Output in HIGH or LOW State –0 GND I V GND ...

Page 5

... Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW ( LOW-to-HIGH (t OSHL ©2006 Fairchild Semiconductor Corporation 74LCX374 Rev. 1.6.0 V (V) Conditions CC 2.3– ...

Page 6

... Dynamic Switching Characteristics Symbol Parameter V Quiet Output Dynamic Peak V OLP V Quiet Output Dynamic Valley V OLV Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT C Power Dissipation Capacitance PD ©2006 Fairchild Semiconductor Corporation 74LCX374 Rev. 1.6.0 V (V) Conditions CC 3.3 C 50pF 2.5 C 30pF 3.3 C 50pF ...

Page 7

... DATA V mo OUT 3-STATE Output Low Enable and Disable Times for Logic Figure 2. Waveforms (Input Characteristics; f =1MHz, t Symbol ©2006 Fairchild Semiconductor Corporation 74LCX374 Rev. 1.6.0 (Generic for LCX Family 500 DUT C L 500 includes probe and jig capacitance) L Test Switch Open ...

Page 8

... Schematic Diagram (Generic for LCX Family) Input Stage Data ESD D2 N+/P– Input Stage P3 Enable ESD D4 N+/P– N3 ©2006 Fairchild Semiconductor Corporation 74LCX374 Rev. 1.6 GTO™ Output D6 N+/P– N5 www.fairchildsemi.com ...

Page 9

... Designator BQX Leader (Start End) Trailer (Hub End) Tape Dimensions inches (millimeters) Reel Dimensions inches (millimeters) Tape Size A 12mm 13.0 (330.0) 0.059 (1.50) ©2006 Fairchild Semiconductor Corporation 74LCX374 Rev. 1.6.0 Tape Number Section Cavities 125 (typ) Carrier 3000 75 (typ 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) ...

Page 10

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 11

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 12

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 13

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 14

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 15

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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