s29ns01gs Meet Spansion Inc., s29ns01gs Datasheet - Page 13

• Manufacturer Part Number: s29ns01gs
• Description: S29ns01gs 1024 Megabit 128 Megabyte 16-bit Data Width, Burst Access, Simultaneous Read/write, 1.8 Volt-only Flash Memory In 65 Nm Mirrorbit Technology
• Manufacturer: Meet Spansion Inc.

5.
April 20, 2009 S29NS-S_00_02
Product Overview
The Eclipse family has a 16 bit (word) wide data bus. All read accesses provide 16 bits of data on each bus
transfer cycle. All writes take 16 bits of data from each bus transfer cycle.
The Eclipse family combines the best features of eXecute In Place (XIP) and Data Storage Flash memories.
The family has the fast random access of XIP Flash along with the high density and fast program speed of
Data Storage Flash. Programming is 10 times faster and Erase is 7 times faster, than traditional NOR Flash.
Random access to any location takes only 115 ns max. After the first word is available the remaining words
within a 16- word (32-Byte) aligned group (Cache Line) around the random access location can be delivered
in a high-speed sequential burst. Linear read burst lengths of 8, or 16-words with wrap around and continuous
burst read are supported.
A wrapped burst begins at the initial location and continues to the end of an 8, or 16 word aligned group then
“wraps-around” to continue at the beginning of the 8, or 16-word aligned group. The burst completes with the
last word before the initial location. Word wrap around burst is generally used for processor cache line fill.
Continuous burst delivers data from the initial word followed by sequential higher address words until the
burst is terminated. At each 16 word (32 byte) aligned boundary additional wait states are inserted as the next
group of 16-words is read. Wait states are indicated by the RDY signal being Low.
The Flash memory array is divided into banks as shown in the above table. A bank is the address range
within which one program, or erase operation may be in progress at the same time as one read operation is in
progress in any other bank of the memory. This multiple bank structure enables Simultaneous Read and
Write (SRW) so that a group of data may be programmed or erased as a background task in one bank, while
code may be executed, or data read, from any other bank.
Each bank is divided into sectors (also referred to as blocks). A sector is the minimum address range of data
which can be erased to an all Ones state. All other sectors are a uniform size of 128 KBytes.
Programming is done via a 512 Byte write buffer. Each 512-Byte aligned group of 512 Bytes is called a page.
It is possible to program from one bit to 512 Bytes, anywhere within a page, in one programming operation.
Each page in a sector may be programmed once before an erase of the sector is required to enable
reprogramming of the same page in the sector.
A bit field programming method may be used to program bit resolution fields within a page. The method may
be used multiple times to incrementally program different bit positions. Bits may only be programmed from a
One (High) to a Zero (Low) state. An erase of the sector where the bit field is located is required to return any,
and all, bits in the sector to the One (erased) state.
D a t a
S29NS01GS
Device
S h e e t
S29NS-S MirrorBit
( P r e l i m i n a r y )
Mbits
1024
®
Eclipse
Mbytes
™
128
Flash Family
Mwords
64
Banks
16
Mbytes / Bank
8
13