s29ns01gs Meet Spansion Inc., s29ns01gs Datasheet - Page 34

• Manufacturer Part Number: s29ns01gs
• Description: S29ns01gs 1024 Megabit 128 Megabyte 16-bit Data Width, Burst Access, Simultaneous Read/write, 1.8 Volt-only Flash Memory In 65 Nm Mirrorbit Technology
• Manufacturer: Meet Spansion Inc.

34
7.8.1.3
Write Buffer (Page) Programming Command
Write Buffer Programming allows the system to write 1 to 256 words in one programming operation. The
Write Buffer Programming command sequence is initiated by first writing the Write Buffer Load command to
the CAP1 address. Next, the system writes the number of word locations minus 1 at the CAP2 address. This
tells the device how many Write Buffer addresses are loaded with data and therefore when to expect the
Program Buffer to Flash confirm command. The Sector Address must match during the Write Buffer Load
command and during the Write Word Count command and the Sector must be unlocked or the operation will
abort and return to the initiating state.
The Write Buffer Programming Command is used to program data within a 512 byte page aligned on a 512
byte boundary. Thus, a full page Write Buffer programming operation must be aligned on a page boundary.
Programming operations of less than a full page may start on any word boundary but may not cross a page
boundary. At the start of a Write Buffer programming operation all locations in the buffer are all ones (FFFFh
words) thus any locations not loaded will not program any ones to zeros.
The system then writes the starting address/data combination. This starting address is the first address/data
pair to be programmed, and selects the write-buffer-page address. The Sector address must match the Write
Buffer Load Sector Address or the operation will abort and return to the initiating state. All subsequent
address/data pairs must be in sequential order. All write buffer addresses must be within the same page. If
the system attempts to load data outside this range, the operation will abort and return to the initiating state.
The counter decrements for each data load operation. Once the specified number of write buffer locations
have been loaded, the system must then write the Program Buffer to Flash command at the CAP1 address.
The device then goes busy as it begins the programming algorithm.
Until the Program Buffer to Flash command is issued, the bank where the write buffer operation will occur
may be read. This allows an interrupt routine to have read access even while the write buffer is being loaded
in order to minimize interrupt latency. After the Program Buffer to Flash command is issued, an interrupt
routine must suspend the program operation before gaining read access to the same bank.
The Embedded Program algorithm automatically programs and verifies the data for the correct data pattern.
The system is not required to provide any controls or timings during these operations. If the incorrect number
of write buffer locations have been loaded and the Program Buffer to Flash command is issued, the operation
will abort and return to the initiating state.
The Write Buffer embedded programming operation can be suspended using the Program Suspend
command. When the Embedded Program algorithm is complete, the device then returns to Erase Suspend,
SSR Lock, Secure Silicon Region, or Idle state. The system can determine the status of the program
operation by reading the Status Register.
Page Byte Offset
0A0h - 0AFh
0C0h - 0CFh
0E0h - 0EFh
1A0h - 1AFh
1C0h - 1CFh
1E0h - 1EFh
000h - 00Fh
020h - 02Fh
040h - 04Fh
060h - 06Fh
080h - 08Fh
100h - 10Fh
120h - 12Fh
140h - 14Fh
160h - 16Fh
180h - 18Fh
S29NS-S MirrorBit
Table 7.14 Bit-Field Programming Page Map
D a t a
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
Status
Status Register on page 25
S h e e t
®
Eclipse
™
Flash Family
( P r e l i m i n a r y )
Page Byte Offset
0D0h - 0DFh
1D0h - 1DFh
0B0h - 0BFh
1B0h - 1BFh
010h - 01Fh
030h - 03Fh
050h - 05Fh
070h - 07Fh
090h - 09Fh
0F0h - 0FFh
110h - 11Fh
130h - 13Fh
150h - 15Fh
170h - 17Fh
190h - 19Fh
1F0h - 1FFh
for information on these status bits.
S29NS-S_00_02 April 20, 2009
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Status