pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 38

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
3.8.3.3
3.8.4
3.8.4.1
Table 3-9. Response to Delayed Read Target Termination
DELAYED READ TARGET TERMINATION RESPONSE
When PI7C8150B initiates a delayed read transaction, the abnormal target responses can be
passed back to the initiator. Other target responses depend on how much data the initiator
requests. Table 3-9 shows the response to each type of target termination that occurs
during a delayed read transaction.
PI7C8150B repeats a delayed read transaction until one of the following conditions is met:
PI7C8150B makes 2
After PI7C8150B makes 2
target bus, PI7C8150B asserts P_SERR_L if the primary SERR_L enable bit is set (bit 8 of
command register for secondary bus) and the delayed-write-non-delivery bit is not set. The
delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register (offset 64h).
PI7C8150B will report system error. See Section 6.4 for a description of system error
conditions.
TARGET TERMINATION INITIATED BY PI7C8150B
PI7C8150B can return a target retry, target disconnect, or target abort to an initiator for
reasons other than detection of that condition at the target interface.
TARGET RETRY
PI7C8150B returns a target retry to the initiator when it cannot accept write data or return
read data as a result of internal conditions. PI7C8150B returns a target retry to an initiator
when any of the following conditions is met:
For delayed write transactions:
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
PI7C8150B completes at least one data transfer.
PI7C8150B receives a master abort.
PI7C8150B receives a target abort.
The transaction is being entered into the delayed transaction queue.
Transaction has already been entered into delayed transaction queue, but target
response has not yet been received.
Target response has been received but has not progressed to the head of the return
queue.
24
(default) read attempts resulting in a response of target retry.
Response
If prefetchable, target disconnect only if initiator requests more data than read
from target. If non-prefetchable, target disconnect on first data phase.
Re-initiate read transaction to target
If initiator requests more data than read from target, return target disconnect to
initiator.
Return target abort to initiator. Set received target abort bit in the target
interface status register. Set signaled target abort bit in the initiator interface
status register.
24
(default) attempts of the same delayed read transaction on the
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B