pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 57

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
Table 6-4. Setting Secondary Interface Master Data Parity Error Detected Bit
Table 6-4 shows setting the data parity detected bit in the status register of secondary
interface. This bit is set under the following conditions:
conditions:
Primary
Parity Bit
0
0
1
0
0
0
1
0
0
0
1
0
X = don’t care
Secondary
Detected
Detected Bit
0
1
0
0
0
1
0
0
0
1
0
0
X= don’t care
Table 6-5 shows assertion of P_PERR_L. This signal is set under the following
The PI7C8150B must be a master on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
The S_PERR_L signal is detected asserted or a parity error is detected on the
secondary bus.
PI7C8150B is either the target of a write transaction or the initiator of a read
transaction on the primary bus.
The parity-error-response bit must be set in the command register of primary interface.
PI7C8150B detects a data parity error on the primary bus or detects S_PERR_L
asserted during the completion phase of a downstream delayed write transaction on the
target (secondary) bus.
Parity
Data
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Primary
Primary
Primary
Primary
Primary
Secondary
Primary
Secondary
Primary
Primary
Primary
Primary
Primary
Secondary
Primary
Secondary
Bus Where Error
Bus Where Error
Was Detected
Was Detected
APRIL 2006 – Revision 2.02
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
Secondary Parity
Secondary Parity
Error Response
Error Response
Primary /
Primary /
PI7C8150B
Bits
Bits