pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 88

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
14.1.39
14.1.40
GPIO DATA AND CONTROL REGISTER – OFFSET 64h
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h
Bit
5
6
7
Bit
11:8
15:12
19:16
23:20
27:24
31:28
Bit
1:0
Function
Delayed Write
Non-Delivery
Delayed Read –
No Data From
Target
Reserved
Function
GPIO Output
Write-1-to-Clear
GPIO Output
Write-1-to-Set
GPIO Output
Enable Write-1-
to-Clear
GPIO Output
Enable Write-1-
to-Set
Reserved
GPIO Input Data
Register
Function
Clock 0 disable
Type
R/W
R/W
R/O
Type
R/WC
R/WS
R/WC
R/WS
R
R/O
Type
R/W
Page 88 of 108
Description
Controls PI7C8150B’s ability to assert P_SERR# when it is unable to
transfer delayed write data after 2
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8150B’s ability to assert P_SERR_L when it is unable
to transfer any read data from the target after 2
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Description
Writing 1 to any of these bits drives the corresponding bit LOW on
the GPIO[3:0] bus if it is programmed as bidirectional. Data is
driven on the PCI clock cycle following completion of the
configuration write to this register. Bit positions corresponding to
GPIO pins that are programmed as input only are not driven. Writing
0 has no effect and will show last the last value written when read.
Reset to 0.
Writing 1 to any of these bits drives the corresponding bit HIGH on
the GPIO[3:0] bus if it is programmed as bidirectional. Data is
driven on the PCI clock cycle following completion of the
configuration write to this register. Bit positions corresponding to
GPIO pins that are programmed as input only are not driven. Writing
0 has no effect and will show last the last value written when read.
Reset to 0.
Writing 1 to and of these bits configures the corresponding
GPIO[3:0] pin as an input only. The output driver is tristated.
Writing 0 to this register has no effect and will reflect the last value
written when read.
Reset to 0.
Writing 1 to and of these bits configures the corresponding
GPIO[3:0] pin as bidirectional. The output driver is enabled and
drives the value set in the output data register (65h). Writing 0 to this
register has no effect and will reflect the last value written when read.
Reset to 0.
Reserved. Returns 0 when read. Reset to 0.
Reads the state of the GPIO[3:0] pins. The state is updated on the PCI
clock following a change in the GPIO[3:0] pins.
Description
If either bit is 0, then S_CLKOUT [0] is enabled.
If both bits are 1, then S_CLKOUT [0] is disabled.
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
24
APRIL 2006 – Revision 2.02
attempts.
24
attempts.
PI7C8150B