pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 58

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
Table 6-5. Assertion of P_PERR_L
Table 6-6. Assertion of S_PERR_L
2
Table 6-6 shows assertion of S_PERR_L that is set under the following conditions:
2
Table 6-7 shows assertion of P_SERR_L. This signal is set under the following conditions:
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
P_PERR_L
1 (de-asserted)
1
0 (asserted)
1
0
1
1
1
0
0
1
1
X = don’t care
S_PERR_L
1 (de-asserted)
0 (asserted)
1
1
1
1
1
0
1
1
0
0
X = don’t care
2
2
PI7C8150B is either the target of a write transaction or the initiator of a read
transaction on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
PI7C8150B detects a data parity error on the secondary bus or detects P_PERR_L
asserted during the completion phase of an upstream delayed write transaction on the
target (primary) bus.
PI7C8150B has detected P_PERR_L asserted on an upstream posted write transaction
or S_PERR_L asserted on a downstream posted write transaction.
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Primary
Secondary
Primary
Secondary
Secondary
Secondary
Secondary
Primary
Secondary
Secondary
Secondary
Secondary
Primary
Primary
Primary
Primary
Secondary
Primary
Primary
Primary
Primary
Secondary
Primary
Secondary
Bus Where Error
Bus Where Error
Was Detected
Was Detected
APRIL 2006 – Revision 2.02
x / x
x / x
1 / x
x / x
1 / x
x / x
x / x
x / x
1 / x
1 / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / x
x / x
x / 1
x / x
x / x
1 / 1
x / 1
Secondary Parity
Secondary Parity
Error Response
Error Response
Primary/
Primary/
PI7C8150B
Bits
Bits