pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 8

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
15
16
17
18
15.1
15.2
16.1
16.2
16.3
16.4
16.5
16.6
17.1
17.2
17.3
17.4
17.5
17.6
18.1
18.2
18.3
14.1.44
14.1.45
14.1.46
14.1.47
14.1.48
14.1.49
14.1.50
14.1.51
14.1.52
14.1.53
14.1.54
14.1.55
15.2.1
15.2.2
15.2.3
15.2.4
16.1.1
16.1.2
BRIDGE BEHAVIOR.................................................................................................................... 95
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER................................................................ 96
ELECTRICAL AND TIMING SPECIFICATIONS................................................................. 102
PACKAGE INFORMATION...................................................................................................... 106
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES .............................................................. 95
ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER).................................... 95
BOUNDARY SCAN ARCHITECTURE..................................................................................... 96
BOUNDARY SCAN INSTRUCTION SET ................................................................................ 98
TAP TEST DATA REGISTERS.................................................................................................. 99
BYPASS REGISTER ................................................................................................................... 99
BOUNDARY-SCAN REGISTER................................................................................................ 99
TAP CONTROLLER ................................................................................................................... 99
MAXIMUM RATINGS ............................................................................................................. 102
DC SPECIFICATIONS.............................................................................................................. 103
AC SPECIFICATIONS.............................................................................................................. 104
66MHZ TIMING........................................................................................................................ 104
33MHZ TIMING........................................................................................................................ 105
POWER CONSUMPTION ........................................................................................................ 105
208-PIN FQFP PACKAGE DIAGRAM .................................................................................... 106
256-BALL PBGA PACKAGE DIAGRAM ............................................................................... 107
PART NUMBER ORDERING INFORMATION...................................................................... 107
MASTER ABORT................................................................................................................ 95
PARITY AND ERROR REPORTING ................................................................................ 95
REPORTING PARITY ERRORS ....................................................................................... 96
SECONDARY IDSEL MAPPING ...................................................................................... 96
TAP PINS ............................................................................................................................ 97
INSTRUCTION REGISTER .............................................................................................. 97
SECONDARY BUS MASTER TIMEOUT COUNTER – OFFSET 80h....................... 91
PRIMARY BUS MASTER TIMEOUT COUNTER – OFFSET 80h............................. 92
CAPABILITY ID REGISTER – OFFSET B0h ............................................................. 92
NEXT POINTER REGISTER – OFFSET B0h ............................................................. 92
SLOT NUMBER REGISTER – OFFSET B0h .............................................................. 92
CHASSIS NUMBER REGISTER – OFFSET B0h ....................................................... 93
CAPABILITY ID REGISTER – OFFSET DCh............................................................. 93
NEXT ITEM POINTER REGISTER – OFFSET DCh ................................................. 93
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh ................. 93
POWER MANAGEMENT DATA REGISTER – OFFSET E0h................................... 94
CAPABILITY ID REGISTER – OFFSET E4h ............................................................. 94
NEXT POINTER REGISTER – OFFSET E4h ............................................................. 94
Page 8 of 108
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B