pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 68

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
10.2
Table 10-1. GPIO Operation
Table 10-2. GPIO Serial Data Format
enabled as an output, the corresponding GPIO output is driven LOW. Writing zeros to
these registers has no effect. The value written to the output register will be driven only
when the GPIO signal is configured as bi-directional. A type 0 configuration write
operation is used to program these fields. The rest value for the output is 0.
SECONDARY CLOCK CONTROL
The PI7C8150B uses the GPIO pins and the MSK_IN signal to input a 16-bit serial data
stream. This data stream is shifted into the secondary clock control register and is used for
selectively disabling secondary clock outputs.
The serial data stream is shifted in as soon as P_RST_L is detected deasserted and the
secondary reset signal, S_RST_L, is detected asserted. The deassertion of S_RST_L is
delayed until the PI7C8150B completes shifting in the clock mask data, which takes 23
clock cycles. After that, the GPIO pins can be used as general-purpose I/O pins.
An external shift register should be used to load and shift the data. The GPIO pins are used
for shift register control and serial data input. Table 10-1 shows the operation of the GPIO
pins.
The data is input through the dedicated input signal, MSK_IN.
The shift register circuitry is not necessary for correct operation of PI7C8150B. The shift
register can be eliminated, and MSK_IN can be tied LOW to enable all secondary clock
outputs or tied HIGH to force all secondary clock outputs HIGH. Table 10-2 shows the
format of the serial stream.
The first 8 bits contain the PRSNT#[1:0] signal values for four slots, and these bits control
the S_CLKOUT[3:0] outputs. If one or both of the PRSNT#[1:0] signals are 0, that
indicates that a card is present in the slot and therefore the secondary clock for that slot is
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
[1:0]
[3:2]
[5:4]
[7:6]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Bit
GPIO Pin
Slot 0 PRSNT#[1:0] or device 0
Slot 1 PRSNT#[1:0] or device 1
Slot 2 PRSNT#[1:0] or device 2
Slot 3 PRSNT#[1:0] or device 3
Device 4
Device 5
Device 6
Device 7
Device 8
PI7C8150B S_CLKIN
Reserved
Reserved
Page 68 of 108
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
Description
Shift register clock output at 33MHz max frequency
Not used
Shift register control
0: Load
1: Shift
Not used
Operation
APRIL 2006 – Revision 2.02
0
1
2
3
4
5
6
7
8
9
NA
NA
S_CLKOUT
PI7C8150B