pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 6

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
5
6
7
8
9
10
11
12
4.3
4.4
5.1
5.2
5.3
5.4
6.1
6.2
6.3
6.4
7.1
7.2
7.3
8.1
8.2
9.1
9.2
9.3
10.1
10.2
10.3
12.1
12.2
12.3
4.3.1
4.3.2
4.4.1
4.4.2
TRANSACTION ORDERING.......................................................................................................... 46
ERROR HANDLING......................................................................................................................... 49
6.2.1
6.2.2
6.2.3
6.2.4
EXCLUSIVE ACCESS ...................................................................................................................... 60
7.2.1
7.2.2
PCI BUS ARBITRATION................................................................................................................. 63
8.2.1
8.2.2
8.2.3
8.2.4
CLOCKS ............................................................................................................................................. 66
GENERAL PURPOSE I/O INTERFACE.................................................................................... 67
PCI POWER MANAGEMENT .................................................................................................... 70
RESET............................................................................................................................................. 70
MEMORY ADDRESS DECODING ........................................................................................... 42
VGA SUPPORT........................................................................................................................... 45
TRANSACTIONS GOVERNED BY ORDERING RULES ....................................................... 46
GENERAL ORDERING GUIDELINES ..................................................................................... 47
ORDERING RULES.................................................................................................................... 48
DATA SYNCHRONIZATION .................................................................................................... 49
ADDRESS PARITY ERRORS .................................................................................................... 49
DATA PARITY ERRORS ........................................................................................................... 50
DATA PARITY ERROR REPORTING SUMMARY................................................................. 55
SYSTEM ERROR (SERR_L) REPORTING............................................................................... 59
CONCURRENT LOCKS ............................................................................................................. 60
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150B .................................................... 60
ENDING EXCLUSIVE ACCESS................................................................................................ 62
PRIMARY PCI BUS ARBITRATION ........................................................................................ 63
SECONDARY PCI BUS ARBITRATION.................................................................................. 63
PRIMARY CLOCK INPUTS....................................................................................................... 66
SECONDARY CLOCK OUTPUTS ............................................................................................ 66
ASYNCHRONOUS MODE......................................................................................................... 66
GPIO CONTROL REGISTERS................................................................................................... 67
SECONDARY CLOCK CONTROL ........................................................................................... 68
LIVE INSERTION ....................................................................................................................... 69
PRIMARY INTERFACE RESET................................................................................................ 70
SECONDARY INTERFACE RESET.......................................................................................... 71
CHIP RESET................................................................................................................................ 71
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ......................... 43
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ................. 44
VGA MODE......................................................................................................................... 45
VGA SNOOP MODE........................................................................................................... 45
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE.......... 50
READ TRANSACTIONS .................................................................................................... 51
DELAYED WRITE TRANSACTIONS............................................................................... 52
POSTED WRITE TRANSACTIONS.................................................................................. 54
LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION ..................................... 60
LOCKED TRANSACTION IN UPSTREAM DIRECTION .............................................. 62
SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER.................... 63
PREEMPTION .................................................................................................................... 65
SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER...................... 65
BUS PARKING.................................................................................................................... 65
Page 6 of 108
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B