pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 67

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
10
10.1
ASYNC_CLKIN and not P_CLK. S_CLKOUT[9] is still connected to S_CLKIN to
provide the same timing as the bus clocks. CFG66/SCAN_EN_H becomes CLK_RATE in
asynchronous mode. Pulling CLK_RATE HIGH sets S_CLKOUT[9:0] equal to
ASYNC_CLKIN. Pulling CLK_RATE LOW sets S_CLKOUT[9:0] to half the frequency
of ASYNC_CLKIN. PI7C8150B will not be able to drive S_M66EN in asynchronous
mode.
GENERAL PURPOSE I/O INTERFACE
The PI7C8150B implements a 4-pin general purpose I/O interface. During normal
operation, device specific configuration registers control the GPIO interface. The GPIO
interface can be used for the following functions:
GPIO CONTROL REGISTERS
During normal operation, the following device specific configuration registers control the
GPIO interface:
These registers consist of five 8-bit fields:
The bottom four bits of the output enable fields control whether each GPIO signal is input
only or bi-directional. Each signal is controlled independently by a bit in each output
enable control field. If a 1 is written to the write-1-to-set field, the corresponding pin is
activated as an output. If a 1 is written to the write-1-to-clear field, the output driver is tri-
stated, and the pin is then input only. Writing zeroes to these registers has no effect. The
reset for these signals is input only.
The input data field is read only and reflects the current value of the GPIO pins. A type 0
configuration read operation to this address is used to obtain the values of these pins. All
pins can be read at any time, whether configured as input only or as bi-directional.
The output data fields also use the write-1-to-set and write-1-to-clear mode. If a 1 is
written to the write-1-to-set field and the pin is enabled as an output, the corresponding
GPIO output is driven HIGH. If a 1 is written to the write-1-to-clear field and the pin is
During secondary interface reset, the GPIO interface can be used to shift in a 16-bit
serial stream that serves as a secondary bus clock disable mask.
Along with the GPIO[3] pin, a live insertion bit can be used to bring the PI7C8150B to
a halt through hardware, permitting live insertion of option cards behind the
PI7C8150B.
The GPIO output data register
The GPIO output enable control register
The GPIO input data register
Write-1-to-set output data field
Write-1-to-clear output data field
Write-1-to-set signal output enable control field
Write-1-to-clear signal output enable control field
Input data field
Page 67 of 108
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B