pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 54

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
6.2.4
For upstream transactions, when the parity error is being passed back from the target bus
and the parity error condition was not originally detected on the initiator bus, the following
events occur:
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when PI7C8150B responds as a target, it
detects a data parity error on the initiator (primary) bus and the following events occur:
Similarly, during upstream posted write transactions, when PI7C8150B responds as a
target, it detects a data parity error on the initiator (secondary) bus, the following events
occur:
During downstream write transactions, when a data parity error is reported on the target
(secondary) bus by the target’s assertion of S_PERR_L, the following events occur:
PI7C8150B asserts S_PERR_L two cycles after the data transfer, if the following are
both true:
PI7C8150B completes the transaction normally.
PI7C8150B asserts P_PERR_L two cycles after the data transfer, if the parity error
response bit is set in the command register of primary interface.
PI7C8150B sets the parity error detected bit in the status register of the primary
interface.
PI7C8150B captures and forwards the bad parity condition to the secondary bus.
PI7C8150B completes the transaction normally.
PI7C8150B asserts S_PERR_L two cycles after the data transfer, if the parity error
response bit is set in the bridge control register of the secondary interface.
PI7C8150B sets the parity error detected bit in the status register of the secondary
interface.
PI7C8150B captures and forwards the bad parity condition to the primary bus.
PI7C8150B completes the transaction normally.
PI7C8150B sets the data parity detected bit in the status register of secondary
interface, if the parity error response bit is set in the bridge control register of the
secondary interface.
The parity error response bit is set in the command register of the primary
interface.
The parity error response bit is set in the bridge control register of the
secondary interface.
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B