ad80164absvz Analog Devices, Inc., ad80164absvz Datasheet - Page 24

• Manufacturer Part Number: ad80164absvz
• Description: Dual, 12-/14-/16-bit,1 Gsps Digital-to-analog Converters
• Manufacturer: Analog Devices, Inc.

AD9776A/AD9778A/AD9779A
THEORY OF OPERATION
The AD9776A/AD9778A/AD9779A combine many features to
make them very attractive DACs for wired and wireless com-
munications systems. The dual digital signal path and dual
DAC structure allow an easy interface with common quadrature
modulators when designing single sideband transmitters. The
speed and performance of the parts allow wider bandwidths
and more carriers to be synthesized than in previously available
DACs. The digital engine uses an innovative filter architecture
that combines the interpolation with a digital quadrature modu-
lator. This allows the parts to perform digital quadrature
frequency upconversions. They also have features that allow
simplified synchronization with incoming data and between
multiple parts.
DIFFERENCES BETWEEN AD9776/AD9778/
AD9779 AND AD9776A/AD9778A/AD9779A
REFCLK Max Frequency vs. Supply
A maximum sample rate of 1100 MHz is supported by
certain restrictions on the DVDD18 and CVDD18 power
supplies. Table 1 lists the valid operating frequencies vs. power
supply voltage.
REFCLK Amplitude
With a differential sinusoidal clock applied to REFCLK, the
PLL on the AD9776/AD9778/AD9779 does not achieve optimal
noise performance unless the REFCLK differential amplitude is
increased to 2 V p-p. Note that if an LVPECL driver is used on the
AD9776/AD9778/AD9779, the PLL gives optimal performance if
the REFCLK amplitude is well within LVPECL specifications
(<1.6 V p-p diff). The design of the PLL on the AD9779A has
been improved, so that even with a sinusoidal clock, the PLL
still achieve optimal amplitude with the swing = 1.6 V p-p.
PLL Lock Ranges
See Table 19 and Figure 75 for PLL lock ranges for the
AD9776A/AD9778A/AD9779A. The individual lock ranges
for the AD9776A/AD9778A/AD9779A PLL are wider than
those for the AD9776/AD9778/AD9779. This means that the
Table 9.
Part No.
AD9779
AD9776A/AD9778A/AD9779A
BW Adjustment
Register 0x0A<4:0>
11111
01111
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PLL Bias Setting
Register 0x09<2:0>
111
011
AD9776A/AD9778A/AD9779A PLL remain in lock in a
given range over a wider temperature range than the AD9776/
AD9778/AD9779.
PLL Optimal Settings
See Table 17, the PLL Loop Filter Bandwidth section, and the
AD9776A/AD9778A/AD9779A PLL Autosearch Feature sec-
tion for the optimal PLL settings for these parts. Table 9 shows
the optimal PLL settings for the AD9776/AD9778/AD9779 and
AD9779A:
Input Data Delay Line, Manual and Automatic
Correction Modes
The AD9776A/AD9778A/AD9779A can be programmed to
sense when the timing margin on the input data falls below
a preset threshold and to take action. The device can be
programmed to either set the IRQ (pin and register) or
automatically reoptimize the timing input data timing.
Input Data Timing
See Table 20 for timing specifications vs. temperature. The
input data timing specifications (setup and hold) have changed
in the AD9776A/AD9778A/AD9779A. They are not the same
as the timing specifications in the AD9776/AD9778/AD9779.
Data Clock Delay Range has been Doubled
In the AD9776/AD9778/AD9779, the input data delay was
controlled by Register 4, Bits<7:4>. At 25°C, the delay was
stepped by approximately 180 ps/increment. In the AD9779A,
an extra bit has been added which effectively doubles the delay
range. This bit is now located at Register 1, Bit 1. The increment/
step on the AD9776A/AD9778A/AD9779A remains at ~180 ps.
Version Register
The version register (Register 0x1F) of the AD9776A/AD9778A/
AD9779A read a value of 0x03. The version register of the
AD9776/AD9778/AD9779 read a value of 0x02.
Optimal PLL Readback Value
Register 0x0A <7:5>
010
011