ad80164absvz Analog Devices, Inc., ad80164absvz Datasheet - Page 28

• Manufacturer Part Number: ad80164absvz
• Description: Dual, 12-/14-/16-bit,1 Gsps Digital-to-analog Converters
• Manufacturer: Analog Devices, Inc.

AD9776A/AD9778A/AD9779A
Table 13. SPI Register Description
Register Name
Comm Register
Digital Control Register
Sync Control Register
Hex
00
00
00
00
00
01
01
01
01
02
02
02
02
02
02
02
02
03
03
00
03
Address
Decimal
7
6
5
4
3
1
7:6
5:2
1
0
7
6
5
4
3
2
1
0
7
6
5:4
Description
SDIO bidirectional
LSB/MSB first
Software reset
Power-down mode
Auto power-down enable
PLL lock indicator (read only)
Filter interpolation factor<1:0>
Filter modulation mode
Data Clock Delay MSB<4>
Zero stuffing enable
Data format
Dual/interleaved data bus mode
Real mode
data clock delay enable
Inverse sinc enable
DATACLK invert
TxEnable invert
Q first
Data clock delay mode
Reserved
Data clock divide ratio<1:0>
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Function
0: use SDIO pin as input data only
1: use SDIO as both input and output data
0: first bit of serial data is MSB of data byte
1: first bit of serial data is LSB of data byte
Bit must be written with a 1, then 0 to soft
reset SPI register map
0: all circuitry is active
1: disable all digital and analog circuitry,
only SPI port is active
Controls auto power-down mode, see the
Power-Down and Sleep Modes section
0: PLL is not locked
1: PLL is locked
00: 1× interpolation
01: 2× interpolation
10: 4× interpolation
11: 8× interpolation
See Table 18 for filter modes
Sets delay of REFCLK in to DATACLK out
0: zero stuffing off
1: zero stuffing on
0: signed binary
1: unsigned binary
0: both input data ports receive data
1: Data Port 1 only receives data
0: enable Q path for signal processing
1: disable Q path data (internal Q channel
clocks disabled, I and Q modulators disabled)
Enables the DATACLK delay feature. More
details on this feature are shown in the
Using Data Delay to Meet Timing
Requirements section
0: inverse sinc filter disabled
1: inverse sinc filter enabled
0: output DATACLK same phase as internal
capture clock
1: output DATACLK opposite phase as
internal capture clock
Inverts the function of TxEnable Pin 39, see
the Interleaved Data Mode section
0: first byte of data is always I data at the
beginning of transmit
1: first byte of data is always Q data at the
beginning of transmit
0: manual error detect mode
1: auto error correct mode
Should always be set to 1
DATACLK output divider value
00: divide by 1
01: divide by 2
10: divide by 4
11: divide by 1
Default
0
0
0
0
0
00
0000
0
0
0
0
0
0
0
0
0
0
00