ad80164absvz Analog Devices, Inc., ad80164absvz Datasheet - Page 45

• Manufacturer Part Number: ad80164absvz
• Description: Dual, 12-/14-/16-bit,1 Gsps Digital-to-analog Converters
• Manufacturer: Analog Devices, Inc.

See Table 20 for specifications of the drift of input data set
up and hold time vs. temperature, as well as the data keep out
window (KOW). Note that although these specifications do
drift, the length of the keep out window, where input data is
invalid, changes very little over temperature.
Table 20. AD9776A/AD9778A/AD9779A Timing
Specifications vs. Temperature
Timing Parameter
DATA with respect to
REFCLK
DATA with respect to
DATACLK
SYNC_I± to REFCLK±
TIMING VALIDATION OF DIGITAL INPUT DATA BUS
Synchronizing the input data bus for valid timing is achieved by
meeting the timing relationships between the digital input data
to REFCLK and DATA out specified in Table 20. If the user is
synchronizing the input data to the DATACLK (Pin 37), the
SYNC_I input signal does not need to be applied and can be
ignored (connect to GND).
±
Temperature
−40°C
+25°C
+85°C
−40°C to +85°C
−40°C
+25°C
+85°C
−40°C to +85°C
−40°C
+25°C
+85°C
−40°C to +85°C
Min
t
(ns)
−0.8
−1.0
−1.1
−0.8
2.5
2.7
3.0
3.0
0.3
0.25
0.15
0.3
S
Min t
(ns)
3.35
3.5
3.8
3.8
−0.05
−0.2
−0.4
−0.05
0.65
0.75
0.90
0.90
H
Max
KOW
(ns)
2.55
2.5
2.7
3.0
2.45
2.5
2.6
2.95
0.95
1.0
1.05
1.2
Rev. 0 Page 45 of 68
SYNCHRONIZATION OF INPUT DATA TO REFCLK
INPUT (PIN 5 AND PIN 6) WITH PLL ENABLED OR
DISABLED
Synchronizing the input data bus to the REFCLK input requires
the use of the SYNC_I input pins (Pin 13 and Pin 14). If the
SYNC_I input is not used, there is a phase ambiguity between
the DATACLK output and the REFCLK input. This ambiguity
is directly related to the interpolation rate in which the AD9776A/
AD9778A/AD9779A are currently operating. Because input data
is latched on the rising edge of DATACLK, it is impossible for
the user to determine on which of multiple internal DACCLK
edges (as an example, one of four edges in 4× interpolation) the
input data actually latches. For the user to specifically deter-
mine the exact edge of the internal DACCLK on which the data
is being latched, a rising edge must be periodically applied to
SYNC_I. The frequency of the SYNC_I signal must be equal
to f
frequency of DATACLK for proper synchronization. There is
no limit on how slow the SYNC_I signal can be driven. As long
as the setup and hold timing relationship between SYNC_I and
REFCLK given in Table 20 is met, the input data is latched on
the immediate next rising edge of REFCLK. Note that a rising
edge of DATACLK occurs concurrently with the next REFCLK
rising edge, after a short propagation delay. Although this
propagation delay is not specified, input data setup and hold
timing information is given with respect to REFCLK and
DATACLK in Figure 94 to Figure 97. Also note that in 1×
interpolation, because there is no phase ambiguity, there is
no need to use the SYNC_I signal.
DAC
/2
N
, N being an integer, and must be no greater than the
AD9776A/AD9778A/AD9779A