ad80164absvz Analog Devices, Inc., ad80164absvz Datasheet - Page 46

• Manufacturer Part Number: ad80164absvz
• Description: Dual, 12-/14-/16-bit,1 Gsps Digital-to-analog Converters
• Manufacturer: Analog Devices, Inc.

AD9776A/AD9778A/AD9779A
VALID TIMING WINDOW, SYNC_I TO REFCLK AND
TO INTERNAL DACCLK
In addition to the timing requirements of SYNC_I with respect
to REFCLK, it is important to understand that the valid timing
window for SYNC_I is limited by the internal DAC sample rate
(see Figure 98). When the t
valid timing window for SYNC_I extends only as far as one
period of the internal DAC sample rate (minus t
Failure to meet this timing specification can possibly result in
erroneous data being latched into the AD9776A/AD9778A/
AD9779A digital inputs.
As an example, if the AD9776A/AD9778A/AD9779A input
data rate is 122.88 MSPS and the REFCLK is the same, with the
AD9776A/AD9778A/AD9779A in 4× interpolation, t
is 1/491.52 MHz or about 2 ns. With a t
+1.0 ns, this gives a valid timing window for SYNC_I of
Also, the timing window of the digital input data to REFCLK
can be moved in increments of one internal DACCLK cycle by
using the DAC clock offset register (Register 0x07 Bits<4:0>).
Because SYNC_I can be run at the same frequency as REFCLK
when the PLL is enabled, it is highly recommend that in this
condition, that REFCLK and SYNC_I originate from the same
source. This limits the variation in time between these two
signals and makes the overall timing budget easier to achieve.
A slight delay may be necessary on the REFCLK path in this
configuration to add more timing margin between REFCLK
and SYNC_I (see Table 20 for timing relationships).
Using Data Delay to Meet Timing Requirements
To meet strict timing requirements at input data rates of up
to 300 MSPS, the AD9776A/AD9778A/AD9779A have a fine
timing feature. Fine timing adjustments are made by program-
ming values into the data clock delay register (Register 0x04,
Bits<7:4>) and Register 0x01 Bit 1. This register can be used
to add delay between the REFCLK input and the DATACLK
output. Figure 99 shows the default delay present when
DATACLK delay is disabled. The DATACLK delay enable bit is
found in Register 0x02, Bit 4. Figure 100 shows the delay
present when DATACLK delay is enabled and set to 00000.
Figure 101 indicates the delay when DATACLK delay is enabled
and set to 01111. Note that the setup and hold times specified
for data to DATACLK are defined for DATACLK delay disabled.
2 ns − 0.8 ns = 1.2 ns
S
and t
H
REFCLK
SYNC_I
requirements are met, the
S
of −0.2 ns and t
Figure 98. Valid Timing Relationship for SYNC_I to REFCLK
S
and t
DAC_SAMPLE
H
).
H
of
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t
DAC_SAMPLE
t
S
t
DAC_SAMPLE
t
H
TEK RUN: 5.00GS/s
TEK RUN: 5.00GS/s
2
1
2
1
Figure 99. Delay from REFCLK to DATACLK with DATACLK Delay Disabled
CH1 1.00VΩ
CH1 1.00VΩ
Figure 100. Delay from REFCLK to DATACLK Out with DATACLK
CH2
CH2
SAMPLE
SAMPLE
500mVΩ
500mVΩ
Delay = 00000
M2.00ns
M2.00ns
CH1
CH1
420mV
420mV
Δ: 4.48ns
@: 40.28ns
Δ: 4.76ns
@: 35.52ns