ad80164absvz Analog Devices, Inc., ad80164absvz Datasheet - Page 47

• Manufacturer Part Number: ad80164absvz
• Description: Dual, 12-/14-/16-bit,1 Gsps Digital-to-analog Converters
• Manufacturer: Analog Devices, Inc.

The difference between the minimum delay shown in
Figure 100 and the maximum delay shown in Figure 101 is
the range programmable via the DATACLK delay register. The
delay (in absolute time) when programming DATACLK delay
between 0000 and 1111 is a linear extrapolation between these
two figures. The typical delays per increment over temperature
are shown in Table 21.
Table 21. Data Delay Line Typical Delays Over Temperature
Delay
Delay Between Disabled and
Average Delay per Increment
The frequency of DATACLK output depends on several pro-
grammable settings. Interpolation, zero stuffing, and input
mode (see Table 22) all have an effect on the REFCLK
frequency. The divisor function between REFCLK and
DATACLK is equal to the values shown in Table 22.
Table 22. REFCLK to DATACLK Divisor Ratio
Interpolation
1
2
4
8
1
2
4
8
1
2
4
8
1
2
4
8
TEK RUN: 5.00GS/s
2
1
Enabled
CH1 1.00VΩ
Figure 101. Delay from REFCLK to DATACLK Out with DATACLK
CH2
Zero Stuffing
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
SAMPLE
500mVΩ
Delay = 01111
M2.00ns
−40°C
630
175
Input Mode
Dual port
Dual port
Dual port
Dual port
Interleaved
Interleaved
Interleaved
Interleaved
Dual port
Dual port
Dual port
Dual port
Interleaved
Interleaved
Interleaved
Interleaved
CH1
+25°C
700
190
420mV
+85°C
740
210
Δ: 7.84ns
@: 32.44ns
Divisor
1
2
4
8
Invalid
1
2
4
2
4
8
16
1
2
4
8
ps
ps
Unit
Rev. 0 Page 47 of 68
In addition to this divisor function, DATACLK can be divided
by up to an additional factor of 4, according to the state of the
DATACLK divide register (Register 0x03, Bits<5:4>). For more
details, see Table 23.
The maximum divisor resulting from the combination of the
values in Table 22, and the DATACLK divide register is 32.
Table 23. Extra DATACLK Divider Ratio
Register 0x03, Bits<5:4>
00
01
10
11
DATA DELAY LINE, ERROR CORRECTION,
MANUAL MODE
As shown in Figure 99, Figure 100, and Figure 101, the
DATACLK delay setting allows the user to adjust the timing
relationship between DATACLK output and the input data. This
provides the user flexibility as it allows the timing relationship
of the input data to the DATACLK output to be programmed
via the SPI port. In addition to simply programming the data
clock delay for a given value, the AD9776A/AD9778A/AD9779A
also allow the user, via SPI readback and a programmable
timing margin, to determine to a good degree of accuracy
how close the present timing is to an invalid region. Note that
because this feature adds delay to the DATACLK output (not
the input data path) signal, it has no effect on the timing
relationship between the input data and REFCLK.
With the error correction enabled in manual mode (Register 3,
Bit 7 = 0), the user can set a timing margin window and then
sweep the DATACLK delay (described previously). The full
span of the delay is equal to about 5.6 ns in 32 increments, so
is about 180 ps/increment as shown in Table 21. The amount
of timing margin that can be set is only four bits (Register 3,
Bits<3:0>), but has the same amount per increment as the
DATACLK delay, roughly 180 ps/increment. Internally, a sampling
clock samples the digital input data, and can sense a transition
on the data inputs. If a data transition is sensed that is close to
the latching DATACLK edge, then a Data Delay IRQ is generated
that can be read from the SPI port Register 19, Bit 7.
This bit must be enabled by Register 0x19, Bit 3. The sense of
Bit 4 of this same register can be used to determine whether the
IRQ is indicating possible set up or hold violation. The Data
Delay IRQ can also be sensed at an external pin (Pin 71). The
internal SYNC IRQ and DATA DELAY IRQ functions are OR’ e d
together at Pin 71 so that an IRQ from either source sets this
pin low. The IRQ does not differentiate between setup and hold
errors so that a full sweep of DATACLK delay may be necessary
to determine which of these two possibilities is causing the IRQ
generation. The margin around the data transition which the
internal circuitry is sensitive to can be adjusted by the window
AD9776A/AD9778A/AD9779A
Divider Ratio
1
2
4
1