ad80164absvz Analog Devices, Inc., ad80164absvz Datasheet - Page 38

• Manufacturer Part Number: ad80164absvz
• Description: Dual, 12-/14-/16-bit,1 Gsps Digital-to-analog Converters
• Manufacturer: Analog Devices, Inc.

AD9776A/AD9778A/AD9779A
PLL LOOP FILTER BANDWIDTH
The loop filter bandwidth of the PLL is programmed via SPI
Register 0x0A, Bits<4:0>. Changing these values switches
capacitors on the internal loop filter. No external loop filter
components are required. This loop filter has a pole at 0 (P1),
and then a zero (Z1) pole (P2) combination. Z1 and P2 occur
within a decade of each other. The location of the zero pole
is determined by Bits<4:0>. For a setting of 00000, the zero
pole occurs near 10 MHz. By setting Bits<4:0> to 11111, the
Z1/P2 combination can be lowered to approximately 1 MHz.
The relationship between Bits<4:0> and the position of the
Z1/P2 between 1 MHz and 10 MHz is linear. However, the
internal components are not low tolerance and can drift by as
much as ±30%.
For optimal performance, the bandwidth adjustment
(Register 0x0A, Bits<4:0>) should be set to 01111 for all
operating modes with PLL enabled. The PLL bias settings
(Register 0x09, Bits<2:0>) should be set to 011. The PLL
control voltage (Register 0x0A, Bits<7:5>) is read back and
is proportional to the dc voltage at the internal loop filter
output. With the PLL bias settings given in this section, the
readback from the PLL control voltage should ideally be 011
or possibly 100 or 010. Anything outside of this range indicates
that the PLL is not operating optimally.
AD9776A/AD9778A/AD9779A PLL AUTOSEARCH
FEATURE
The AD9776A/AD9778A/AD9779A have an autosearch feature
that determines the optimal band for the PLL. To enable the
autosearch mode, set Register 0x08, Bits<7:2> to 11111b (63),
and read back the value from Register 0x08, Bits<7:2>. Auto-
search mode is intended to find the optimal PLL band only,
after which the same settings should be applied in manual
mode. It is not recommended that the PLL be set to auto-
search mode during regular operation.
Figure 75. Typical PLL Band Select vs. Frequency over Temperature
61
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There are two ways in which the autosearch feature can be used.
The first method is if the unit is in an environment where it is
always started at ~25°C. In this case, the autosearch feature
can be used to read back the optimal lock range value, and this
value can then be immediately programmed into the lock range
register. Started and programmed under this condition, the
AD9776A/AD9778A/AD9779A are guaranteed to hold PLL
lock over the entire operating temperature range. In this situation,
autosearch only needs to be enabled when the unit is powered
on. After the initial readback and programming the readback
value into the lock range register, disable autosearch.
The second method for programming the PLL lock range in
the AD9776A/AD9778A/AD9779A should be used if the unit
is expected to start up under more extreme temperature shifts.
For the AD9776A/AD9778A/AD9779A PLL to remain locked
over the complete operating temperature range, the user should
perform the following test in the factory at 25°C:
Enable the autosearch mode and read back the optimal value
from the lock range register. Store this value in system memory
(RAM, FPGA, ASIC).
As long as the unit is always programmed with this stored 25°C
value on start-up, the PLL in the AD9776A/AD9778A/AD9779A
is guaranteed to remain locked over the full temperature range
of the part. This is true regardless of what the start-up tempera-
ture is of the unit.
Note that the autosearch mode only gives an accurate lock
range, valid over the entire temperature range if the autosearch
mode is enabled at  2 5°C. When the lock range at 25°C is deter-
mined and the value is stored, the autosearch mode should then
be disabled. See AN-919 at
information for valid lock ranges over temperature.
FULL-SCALE CURRENT GENERATION
Internal Reference
Full-scale current on the I DAC and Q DAC can be set from
8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference
is used to set up a current in an external resistor connected to
I120 (Pin 75). A simplified block diagram of the reference
circuitry is shown in Figure 76. The recommended value for
the external resistor is 10 kΩ, which sets up an I
resistor of 120 μA, which in turn provides a DAC output full-
scale current of 20 mA. Because the gain error is a linear function
of this resistor, a high precision resistor improves gain matching
to the internal matching specification of the devices. Internal
current mirrors provide a current-gain scaling, where I DAC
or Q DAC gain is a 10-bit word in the SPI port register
(Register 0x0B, Register 0x0C, Register 0x0F, and Register 0x10).
The default value for the DAC gain registers gives an I
approximately 20 mA. I
I
FS
=
1.2
R
V
×
⎛
⎜
⎝
27
12
+
FS
⎛
⎜
⎝
1024
is equal to
6
www.analog.com
×
DAC gain
⎞
⎟
⎠
⎞
⎟
⎠
×
for more
32
REFERENCE
FS
of
in the