ad80164absvz Analog Devices, Inc., ad80164absvz Datasheet - Page 27

• Manufacturer Part Number: ad80164absvz
• Description: Dual, 12-/14-/16-bit,1 Gsps Digital-to-analog Converters
• Manufacturer: Analog Devices, Inc.

SPI REGISTER MAP
Table 12.
Register
Name
Comm
Digital
Control
Sync
Control
PLL
Control
Misc
Control
I DAC
Control
Register
AUX
DAC1
Control
Register
Q DAC
Control
Register
AUX
DAC2
Control
Register
Interrupt
Register
Version
Register
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
to
0x18
0x19
0x1F
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19 to 24
25
31
Bit 7
SDIO
Bidirectional
Filter Interpolation Factor<1:0>
Data Format
Data Clock
Delay Mode
Sync
Receiver
Enable
PLL Enable
I DAC Sleep
Auxiliary
DAC1 Sign
Q DAC Sleep
Auxiliary
DAC2 Sign
Data Delay
IRQ
PLL Control Voltage Range<2:0> (Read-Only)
Bit 6
LSB/MSB First
Dual/Interleaved
Data Bus Mode
Reserved, Should
Always Be Set High
Sync Driver
Enable
PLL VCO Divider Ratio<1:0>
I DAC Power
Down
Auxiliary DAC1
Current Direction
Q DAC Power-
Down
Auxiliary DAC2
Current Direction
Data Clock Delay LSBs<3:0>
Sync Delay IRQ
Sync Input Delay<3:0>
Sync Out Delay<3:0>
PLL Band Select<5:0>
Rev. 0 Page 27 of 68
Bit 5
Software
Reset
Real Mode
Data Clock Divide
Ratio<1:0>
Sync
Triggering
Edge
Auxiliary
DAC1
Power-
Down
Auxiliary
DAC2
Power-
Down
Q DAC Gain Adjustment<7:0>
I DAC Gain Adjustment<7:0>
Auxiliary DAC1 Data <7:0>
Auxiliary DAC2 Data<7:0>
Filter Modulation Mode<3:0>
Bit 4
Power-
Down
Mode
Data
Clock
Delay
Enable
PLL Loop
Divide
Ratio<1:0>
Setup
Status
IRQ
Version<7:0>
Reserved
Bit 3
Auto
Power-
Down
Enable
Inverse
Sinc
Enable
PLL Loop Bandwidth Adjustment<4:0>
Data
Delay
IRQ
Enable
Input Sync Pulse Frequency Ratio<2:0>
PLL Bias Setting<2:0>
Input Sync Pulse Timing Error Tolerance<3:0>
Output Sync Pulse Divide<2:0>
DAC Clock Offset<4:0>
AD9776A/AD9778A/AD9779A
Data Delay Timing Margin<3:0>
Bit 2
DATACLK
Invert
Sync Delay
IRQ Enable
Bit 1
PLL Lock
Indicator
(Read
Only)
Data
Clock
Delay
MSB<4>
TxEnable
Invert
Adjustment<9:8>
Adjustment<9:8>
Auxiliary DAC1
Auxiliary DAC2
PLL VCO AGC
Q DAC Gain
I DAC Gain
Data<9:8>
Data<9:8>
Gain<1:0>
Bit 0
Zero
Stuffing
Enable
Q First
Sync Out
Delay<4>
Sync Input
Delay<4>
Loopback
Internal
Sync
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE7
0x52
0x1F
0xF9
0x01
0x00
0x00
0xF9
0x01
0x00
0x00
0x00
0x03
Def.