ad80164absvz Analog Devices, Inc., ad80164absvz Datasheet - Page 36

• Manufacturer Part Number: ad80164absvz
• Description: Dual, 12-/14-/16-bit,1 Gsps Digital-to-analog Converters
• Manufacturer: Analog Devices, Inc.

AD9776A/AD9778A/AD9779A
DRIVING THE REFCLK INPUT
The REFCLK input requires a low jitter differential drive
signal. It is a PMOS input differential pair powered from
the 1.8 V supply, therefore, it is important to maintain the
specified 400 mV input common-mode voltage. Each input
pin can safely swing from 200 mV p-p to 1 V p-p about the
400 mV common-mode voltage. Although these input levels
are not directly LVDS-compatible, REFCLK can be driven by
an offset ac-coupled LVDS signal, as shown in Figure 71.
If a clean sine clock is available, it can be transformer-coupled
to REFCLK, as shown in Figure 71. Use of a CMOS or TTL
clock is also acceptable for lower sample rates. It can be routed
through a CMOS to LVDS translator, then ac-coupled, as
described in this section. Alternatively, it can be transformer-
coupled and clamped, as shown in Figure 72.
A simple bias network for generating V
Figure 73. It is important to use CVDD18 and CGND for
the clock bias circuit. Any noise or other signal that is coupled
onto the clock is multiplied by the DAC digital input signal and
can degrade DAC performance.
TTL OR CMOS
CLK INPUT
287Ω
1kΩ
LVDS_P_IN
LVDS_N_IN
Figure 72. TTL or CMOS REFCLK Drive Circuit
Figure 73. REFCLK V
Figure 71. LVDS REFCLK Drive Circuit
0.1µF
0.1µF
0.1µF
0.1µF
50Ω
50Ω
1nF
CM
Generator Circuit
V
V
CM
CM
1nF
CM
50Ω
= 400mV
50Ω
= 400mV
is shown in
REFCLK–
REFCLK+
BAV99ZXCT
HIGH SPEED
DUAL DIODE
V
CM
CVDD18
CGND
= 400mV
REFCLK+
REFCLK–
Rev. 0 | Page 36 of 68
INTERNAL PLL CLOCK MULTIPLIER/CLOCK
DISTRIBUTION
The internal clock structure on the devices allows the user to
drive the differential clock inputs with a clock at 1× or an integer
multiple of the input data rate up to the DAC output sample
rate. An internal PLL provides input clock multiplication and
provides all the internal clocks required for the interpolation
filters and data synchronization.
The internal clock architecture is shown in Figure 74. The
reference clock is the differential clock at Pin 5 and Pin 6.
This clock input can be run differentially or singled-ended
by driving Pin 5 with a clock signal and biasing Pin 6 to the
midswing point of the signal at Pin 5. The clock architecture
can be run in the following configurations:
PLL Enabled (Register 0x09, Bit 7 = 1)
The PLL enable switch shown in Figure 74 is connected to
the junction of the N
dividers (PLL loop divide ratio). Divider N
interpolation rate of the DAC, and the ratio N
the ratio of reference clock/input data rate. The VCO runs
optimally over the range of 1.0 GHz to 2.0 GHz, so that N
keeps the speed of the VCO within this range, although the
DAC sample rate can be lower. The loop filter components are
entirely internal and no external compensation is necessary.
PLL Disabled (Register 0x09, Bit 7 = 0)
The PLL enable switch shown in Figure 74 is connected to the
reference clock input. The differential reference clock input is
the same as the DAC output sample rate. N
interpolation rate.
REFERENCE CLOCK
(PIN 5 AND PIN 6)
PLL ENABLE
DETECTION
PHASE
0x09 <7>
Figure 74. Internal Clock Architecture
DIVIDE RATIO
0x09 <4:3>
PLL LOOP
1
dividers (PLL VCO divide ratio) and N
÷N
2
INTERNAL DAC SAMPLE
LOOP FILTER
BANDWIDTH
0x0A <4:0>
INTERNAL
FILTER
LOOP
RATE CLOCK
DIVIDE RATIO
0x09 <6:5>
PLL VCO
÷N
0x01 <7:6>
1
÷N
VCO RANGE
0x08 <7:2>
3
VCO
ADC
3
3
DATACLK OUT (PIN 37)
determines the
determines the
INTERPOLATION
3
/N
RATE
DAC
2
0x0A <7:5>
PLL CONTROL
VOLTAGE RANGE
determines
1
2