mm74c74 Fairchild Semiconductor, mm74c74 Datasheet

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mm74c74

Manufacturer Part Number
mm74c74
Description
Dual D-type Flip-flop
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2002 Fairchild Semiconductor Corporation
MM74C74M
MM74C74N
MM74C74
Dual D-Type Flip-Flop
General Description
The MM74C74 dual D-type flip-flop is a monolithic comple-
mentary MOS (CMOS) integrated circuit constructed with
N- and P-channel enhancement transistors. Each flip-flop
has independent data, preset, clear and clock inputs and Q
and Q outputs. The logic level present at the data input is
transferred to the output during the positive going transition
of the clock pulse. Preset or clear is independent of the
clock and accomplished by a low level at the preset or clear
input.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Note: A logic “0” on clear sets Q to logic “0”.
Order Number
A logic “0” on preset sets Q to logic “1”.
Package Number
Top View
M14A
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
DS005885
Features
Applications
• Automotive
• Data terminals
• Instrumentation
• Medical electronics
• Alarm system
• Industrial electronics
• Remote metering
• Computers
Truth Table
Note 1: No change in output from previous state.
Supply voltage range:
Tenth power TTL compatible: Drive 2 LPT
High noise immunity: 0.45 V
Low power: 50 nW (typ.)
Medium speed operation: 10 MHz (typ.) with 10V
supply
Preset
Package Description
0
0
1
1
Clear
0
1
0
1
3V to 15V
October 1987
Revised May 2002
CC
(Note 1)
(typ.)
Q
Q
0
1
0
n
n
www.fairchildsemi.com
2
L loads
(Note 1)
Q
Q
0
0
1
n
n

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mm74c74 Summary of contents

Page 1

... MM74C74 Dual D-Type Flip-Flop General Description The MM74C74 dual D-type flip-flop is a monolithic comple- mentary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors. Each flip-flop has independent data, preset, clear and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse ...

Page 2

Logic Diagram www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings Voltage at Any Pin (Note 2) 0. Operating Temperature Range Storage Temperature Range Power Dissipation Dual-In-Line Small Outline Lead Temperature (Soldering, 10 seconds) Operating V Range CC V (Max Electrical Characteristics Min/Max limits ...

Page 4

AC Electrical Characteristics pF, unless otherwise noted A L Symbol Parameter C Input Capacitance IN t Propagation Delay Time Logical “0” Logical “1” pd0 t from Clock ...

Page 5

Switching Time Waveform Test Circuit CMOS to CMOS 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow www.fairchildsemi.com Package Number M14A 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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