mc145156 Lansdale Semiconductor, Inc., mc145156 Datasheet - Page 10

• Manufacturer Part Number: mc145156
• Description: Pll Frequency Synthesizer Family
• Manufacturer: Lansdale Semiconductor, Inc.

ML145155
INPUT PINS
f in
Frequency Input (PDIP – Pin 9, SOG – Pin 10)
derived from loop VCO and is AC coupled into the device. For
larger amplitude signals (standard CMOS logic levels) DC
coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (PDIP – Pins 18, 1, 2; SOG –
Pins 20, 1, 2)
possible divide values for the total reference divider, as defined
by the table below:
Shift Register Clock, Serial Data Inputs
(PDIP – Pins 10, 11; SOG – Pins 11, 12)
16–bit shift register. The Data input provides programming
information for the 14–bit ÷ N counter and the two switch
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Input to the ÷ N portion of the synthesizer. f in is typically
These three inputs establish a code defining one of eight
CLK, DATA
Each low–to–high transition clocks one bit into the on–chip
RA2
0
0
0
0
1
1
1
1
OSC out
REF out
Reference Address Code
OSC in
DATA
ENB
CLK
f in
PIN DESCRIPTIONS
RA1
0
0
1
1
0
0
1
1
RA0
0
1
0
1
0
1
0
1
V DD
Divide
Divide
Value
Total
1024
2048
3668
4096
6144
8192
512
16
RA2
RA1
RA0
ML145155 BLOCK DIAGRAM
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14 x 8 ROM REFERENCE DECODER
signals SW1 and SW2. The entry format is as follows:
ENB
Latch Enable Input (PDIP – Pin 12, SOG – Pin 13)
ister into the latches, and to the programmable counter inputs,
and the switch outputs SW1 and SW2. When low (0), ENB
inhibits the above action and thus allows changes to be made
in the shift register data without affecting the counter program-
ming and switch outputs. An on–chip pull–up establishes a
continuously high level for ENB when no external signal is
applied. ENB is normally low and is pulsed high to transfer
data to the latches.
OSC in , OSC out
Reference Oscillator Input/Output (PDIP – Pins 17, 16;
SOG – Pins 19, 18)
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
nected from OSC in to ground and OSC out to ground. OSC in
may also serve as the input for an externally–generated refer-
ence signal. This signal is typically ac coupled to OSC in , but
for larger amplitude signals (standard CMOS logic levels) DC
coupling may also be used. In the external reference mode, no
connection is required to OSC out .
14–BIT SHIFT REGISTER
14–BIT
14–BIT
When high (1), ENB transfers the contents of the shift reg-
These pins form an on–chip reference oscillator when con-
÷
÷
LATCH
R COUNTER
R COUNTER
LAST DATA BIT IN (BIT NO. 16)
14
14
14
÷
N COUNTER BITS
f R
f V
LANSDALE Semiconductor, Inc.
FIRST DATA BIT IN (BIT NO. 1)
2–BIT SHIFT
DETECTOR
REGISTER
DETECTOR
DETECT
LATCH
PHASE
PHASE
LOCK
A
B
LD
PD out
φ V
φ R
SW2
SW1
Issue A