mc145156 Lansdale Semiconductor, Inc., mc145156 Datasheet - Page 11

• Manufacturer Part Number: mc145156
• Description: Pll Frequency Synthesizer Family
• Manufacturer: Lansdale Semiconductor, Inc.

LANSDALE Semiconductor, Inc.
OUTPUT PINS
PD out
Phase Detector A Output (PDIP, SOG – Pin 6)
signal. Double–ended outputs are also available for this pur-
pose (see φV and φR).
ance State
φR, φV
Phase Detector B Outputs (PDIP, SOG – Pins 4, 3)
a loop–error signal. A single–ended output is also available for
this purpose (see PD out ).
leading, then error information is provided by f V pulsing low.
f R remains essentially high.
lagging, then error information is provided by f R pulsing low.
f V remains essentially high.
f V and f R remain high except for a small minimum time peri-
od when both pulse low in phase.
LD
Lock Detector Output (PDIP – Pin 8, SOG – Pin 9)
Page 11 of 35
Three–state output of phase detector for use as loop error
Frequency f V > f R or f V Leading: Negative Pulses
Frequency f V < f R or f V Lagging: Positive Pulses
Frequency f V = f R and Phase Coincidence: High–Imped-
These phase detector outputs can be combined externally for
If frequency f V is greater than f R or if the phase of f V is
If the frequency f V is less than f R or if the phase of f V is
If the frequency of f V = f R and both are in phase, then both
Essentially a high level when loop is locked (f R , f V of same
* The φ R and φ V outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop – Low–Pass Filter Design page
for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common
mode input range of the op amp used in the combiner/loop filter.
FRONT END
TUNER OR
UHF/VHF
CATV
Figure 1. Microprocessor–Controlled TV/CATV Tuning System with Serial Interface
PRESCALER
KEYBOARD
MC120xx
TYPICAL APPLICATIONS
www.lansdale.com
f in
DATA
ML145155
CLK
ML145155
phase and frequency). LD pulses low when loop is out of lock.
SW1, SW2
Band Switch Outputs (PDIP – Pins 13, 14; SOG – Pins 14, 15)
sponding to data bits numbers one and two. These outputs can
be tied through external resistors to voltages as high as 15 V,
independent of the V DD supply voltage. These are typically
used for band switch functions. A logic 1 causes the output to
assume a high–impedance state, while a logic 0 causes the out-
put to be low.
REF out
Buffered Reference Oscillator Output (PDIP, SOG – Pin 15)
provided reference–input signal.
POWER SUPPLY
VDD
Positive Power Supply (PDIP, SOG – Pin 5)
from + 3 to + 9 V with respect to V SS .
VSS
Negative Power Supply (PDIP, SOG – Pin 7)
ground.
4.0 MHz
SW1 and SW2 provide latched open–drain outputs corre-
Buffered output of on–chip reference oscillator or externally
The positive power supply potential. This pin may range
The most negative supply potential. This pin is usually
MPU/MCU
CMOS
ENB
φ R
φ V
3
LED DISPLAY
MC14489
+
–
1/2 MC1458*
ML145155
Issue A