mc145156 Lansdale Semiconductor, Inc., mc145156 Datasheet - Page 21

• Manufacturer Part Number: mc145156
• Description: Pll Frequency Synthesizer Family
• Manufacturer: Lansdale Semiconductor, Inc.

LANSDALE Semiconductor, Inc.
INPUT PINS
f in Frequency Input (Pin 8)
this input decrements the ÷ A and ÷ N counters. This input has
an inverter biased in the linear region to allow use with AC
coupled signals as low as 500 mV p–p. For larger amplitude
signals (standard CMOS logic levels), DC coupling may be
used.
CLK, DATA
Shift Clock, Serial Data Inputs (Pins 9, 10)
data into the on–chip shift registers. The last data bit entered
determines which counter storage latch is activated; a logic 1
selects the reference counter latch and a logic 0 selects the
Page 21 of 35
÷ A, ÷ N counter latch. The data entry format is as follows:
Input frequency from VCO output. A rising edge signal on
Each low–to–high transition of the CLK shifts one bit of
OSC out
REF out
OSC in
DATA
ENB
CLK
f in
PIN DESCRIPTIONS
FIRST DATA BIT INTO SHIFT REGISTER
CONTROL
1–BIT
S/R
÷
R
ML145158 BLOCK DIAGRAM
www.lansdale.com
÷
7–BIT
COUNTER
A COUNTER
7–BIT S/R
LATCH
REFERENCE COUNTER LATCH
÷
7
7
14–BIT SHIFT REGISTER
14–BIT
A
ENB
Latch Enable Input (Pin 11)
ter into the reference divider or ÷ N, ÷ A latches depending on
the control bit. The reference divider latches are activated if the
control bit is at a logic high and the ÷ N, ÷ A latches are acti-
vated if the control bit is at a logic low. A logic low on this pin
allows the user to change the data in the shift registers without
affecting the counters. ENB is normally low and is pulsed high
to transfer data to the latches.
OSC in , OSC out
Reference Oscillator Input/Output (Pins 1, 2)
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
nected from OSC in to ground and OSC out to ground. OSC in
may also serve as the input for an externally–generated refer-
ence signal. This signal is typically AC coupled to OSC in , but
for larger amplitude signals (standard CMOS logic levels) DC
coupling may also be used. In the external reference mode, no
connection is required to OSC out .
CONTROL LOGIC
A logic high on this pin latches the data from the shift regis-
These pins form an on–chip reference oscillator when con-
÷
R COUNTER
14
14
÷
10–BIT
COUNTER
10–BIT S/R
N COUNTER
LATCH
÷
÷
A
10
10
N
FIRST DATA BIT INTO SHIFT REGISTER
DETECTOR
DETECTOR
DETECT
PHASE
PHASE
LOCK
÷
B
A
N
f R
LD
PD out
φ V
φ R
f V
MC
ML145158
Issue A