mc145156 Lansdale Semiconductor, Inc., mc145156 Datasheet - Page 6

• Manufacturer Part Number: mc145156
• Description: Pll Frequency Synthesizer Family
• Manufacturer: Lansdale Semiconductor, Inc.

LANSDALE Semiconductor, Inc.
INPUT PINS
f in
Frequency Input (Pin 1)
f in is typically derived from a dual–modulus prescaler and is
AC coupled into the device. For larger amplitude signals (stan-
dard CMOS logic levels) DC coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (Pins 4, 5, 6)
possible divide values for the total reference divider. The total
reference divide values are as follows:
N0 – N9
N Counter Programming Inputs (Pins 11 – 20)
counter when it reaches the count of 0. N0 is the least signifi-
cant digit and N9 is the most significant. Pull–up resistors en-
sure that inputs left open remain at a logic 1 and require only a
SPST switch to alter data to the zero state.
A0 – A5
A Counter Programming Inputs(Pins 23, 21, 22, 24, 25, 10)
require a logic 0 on the MC output (see Dual–Modulus Pres-
caling section). The A inputs all have internal pull–up resis-
Page 6 of 35
Input to the positive edge triggered ÷ N and ÷ A counters.
These three inputs establish a code defining one of eight
The N inputs provide the data that is preset into the ÷ N
The A inputs define the number of clock cycles of f in that
RA2
0
0
0
0
1
1
1
1
Reference Address Code
NOTE: N0 – N9, A0 – A5, and RA0 – RA2 have pull–up resistors that are not shown.
OSC out
OSC in
f in
PIN DESCRIPTIONS
RA1
0
0
1
1
0
0
1
1
RA0
0
1
0
1
0
1
0
1
RA2
RA1
RA0
6–BIT
A5
Divide
Divide
Value
Total
1024
1160
2048
128
256
512
64
÷
8
A3 A2
A COUNTER
ML145152 BLOCK DIAGRAM
12 x 8 ROM REFERENCE DECODER
www.lansdale.com
A0
12–BIT
CONTROL
÷
LOGIC
R COUNTER
N0
tors that ensure that inputs left open will remain at a logic 1.
OSC in , OSC out
Reference Oscillator Input/Output (Pins 27, 26)
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
nected from OSC in to ground and OSC out to ground. OSC in
may also serve as the input for an externally generated refer-
ence signal. This signal is typically AC coupled to OSC in , but
for larger amplitude signals (standard CMOS logic levels) DC
coupling may also be used. In the external reference mode, no
connection is required to OSC out .
OUTPUT PINS
φR,φV
Phase Detector B Outputs (Pins 7, 8)
a loop–error signal.
leading, then error information is provided by φV pulsing low.
φR remains essentially high.
lagging, then error information is provided by φR pulsing low.
φV remains essentially high.
φV and φR remain high except for a small minimum time peri-
od when both pulse low in phase.
controlling an external dual–modulus prescaler. The MC level
will be low at the beginning of a count cycle and will remain
low until the ÷ A counter has counted down from its pro-
grammed value. At this time, MC goes high and remains high
until the ÷ N counter has counted the rest of the way down
from its programmed value (N – A additional counts since
both ÷ N and ÷ A are counting down during the first portion of
the cycle). MC is then set back low, the counters preset to
12
These pins form an on–chip reference oscillator when con-
These phase detector outputs can be combined externally for
If the frequency f V is greater than f R or if the phase of f V is
If the frequency f V is less than f R or if the phase of f V is
If the frequency of f V = f R and both are in phase, then both
MC
Dual–Modulus Prescale Control Output (Pin 9)
Signal generated by the on–chip control logic circuitry for
10–BIT
N2
÷
N4 N5
N COUNTER
N7
N9
DETECTOR
DETECT
PHASE
LOCK
LD
MC
φ V
φ R
ML145152
Issue A