mc145156 Lansdale Semiconductor, Inc., mc145156 Datasheet - Page 29

• Manufacturer Part Number: mc145156
• Description: Pll Frequency Synthesizer Family
• Manufacturer: Lansdale Semiconductor, Inc.

LANSDALE Semiconductor, Inc.
CRYSTAL OSCILLATOR CONSIDERATIONS
ence frequency to Motorola's or Lansdale’s CMOS frequency
synthesizers.
Use of a Hybrid Crystal Oscillator
oscillators (TCXOs) or crystal–controlled data clock oscilla-
tors provide very stable reference frequencies. An oscillator
capable of sinking and sourcing 50 µA at CMOS logic levels
may be direct or DC coupled to OSC in . In general, the highest
frequency capability is obtained utilizing a direct–coupled
square wave having a rail–to–rail (V DD to V SS ) voltage
swing. If the oscillator does not have CMOS logic levels on the
outputs, capacitive or AC coupling to OSC in may be used.
OSC out , an unbuffered output, should be left floating.
oscillators, please consult the latest version of the eem Elec-
tronic Engineers Master Catalog, the Gold Book, or similar
publications.
Design an Off–Chip Reference
specifically developed for crystal oscillator applications, such
as the ML12061 MECL device. The reference signal from the
MECL device is AC coupled to OSC in . For large amplitude
signals (standard CMOS logic levels), DC coupling is used.
OSC out , an unbuffered output, should be left floating. In gen-
eral, the highest frequency capability is obtained with a di-
rect–coupled square wave having rail–to–rail voltage swing.
Use of the On–Chip Oscillator Circuitry
propriate crystal may be used to provide a reference source fre-
quency. A fundamental mode crystal, parallel resonant at the
desired operating frequency, should be connected as shown in
Figure 10.
capacitance, C L , which does not exceed 32 pF for frequencies to
approximately 8.0 MHz, 20 pF for frequencies in the area of 8.0 to
15 MHz, and 10 pF for higher frequencies. These are guidelines
that provide a reasonable compromise between IC capacitance,
drive capability, swamping variations in stray and IC input/output
capacitance, and realistic C L values. The shunt load capacitance,
C L , presented across the crystal can be estimated to be:
Page 29 of 35
The following options may be considered to provide a refer-
Commercially available temperature–compensated crystal
For additional information about TCXOs and data clock
The user may design an off–chip crystal oscillator using ICs
The on–chip amplifier (a digital inverter) along with an ap-
For V DD = 5.0 V , the crystal should be specified for a loading
Figure 10. Pierce Crystal Oscillator Circuit
* May be deleted in certain cases. See text.
OSC in
C1
R f
C2
R1*
SYNTHESIZER
FREQUENCY
OSC out
www.lansdale.com
portion or all of C1 variable. The crystal and associated com-
ponents must be located as close as possible to the OSC in and
OSC out pins to minimize distortion, stray capacitance, stray
inductance, and startup stabilization time. In some cases, stray
capacitance should be added to the value for C in and C out .
crystal, Re, in Figure 12. The drive level specified by the crys-
tal manufacturer is the maximum stress that a crystal can with-
stand without damage or excessive shift in frequency. R1 in
Figure 10 limits the drive level. The use of R1 may not be nec-
essary in some cases (i.e., R1 = 0 Ω).
overdrive the crystal, monitor the output frequency as a func-
tion of voltage at OSC out . (Care should be taken to minimize
loading.) The frequency should increase very slightly as the
DC supply voltage is increased. An overdriven crystal will
decrease in frequency or become unstable with an increase in
supply voltage. The operating supply voltage must be reduced
or R1 must be increased in value if the overdriven condition
exists. The user should note that the oscillator start–up time is
proportional to the value of R1.
CMOS inverters, many crystal manufacturers have developed
expertise in CMOS oscillator design with crystals. Discussions
with such manufacturers can prove very helpful (see Table 1).
The oscillator can be “trimmed” on–frequency by making a
Power is dissipated in the effective series resistance of the
To verify that the maximum DC supply voltage does not
Through the process of supplying crystals for use with
C1 and C2 = external capacitors (see Figure 10)
where
1
NOTE: Values are supplied by crystal manufacturer
Figure 11. Parasitic Capacitances of the Amplifier
C out = 6 pF (see Figure 11)
C in = 5 pF (see Figure 11)
C O = the crystal's holder capacitance
C a = 1 pF (see Figure 11)
Figure 12. Equivalent Crystal Networks
(parallel resonant crystal).
C L =
(see Figure 12)
C in
2
C in + C out
C in C out
1
1
+ C a + C o + C1
C a
R e
R S
X e
C out
C O
L S
C1 + C2
•
2
C2
C S
ML1451xx
2
Issue A