mc145156 Lansdale Semiconductor, Inc., mc145156 Datasheet - Page 14

• Manufacturer Part Number: mc145156
• Description: Pll Frequency Synthesizer Family
• Manufacturer: Lansdale Semiconductor, Inc.

ML145156
INPUT PINS
f in
Frequency Input (Pin 10)
f in is typically derived from a dual–modulus prescaler and is
AC coupled into the device. For larger amplitude signals (stan-
dard CMOS logic levels), DC coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (Pins 20, 1, 2)
possible divide values for the total reference divider, as defined
by the table below:
CLK, DATA
Shift Register Clock, Serial Data Inputs (Pins 11, 12)
19–bit shift register. The data input provides programming in-
formation for the 10–bit ÷ N counter, the 7–bit ÷ A counter,
and the two switch signals SW1 and SW2. The entry format is
as follows:
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Input to the positive edge triggered ÷ N and ÷ A counters.
These three inputs establish a code defining one of eight
Each low–to–high transition clocks one bit into the on–chip
RA2
OSC out
REF out
0
0
0
0
1
1
1
1
OSC in
Reference Address Code
DATA
ENB
CLK
MC
f in
PIN DESCRIPTIONS
V DD
RA1
0
0
1
1
0
0
1
1
RA0
0
1
0
1
0
1
0
1
RA2
RA1
RA0
7–BIT SHIFT REGISTER
÷
7–BIT
Divide
Divide
A COUNTER LATCH
Value
Total
1000
1024
2048
128
256
640
64
8
÷
A COUNTER
ML145156 BLOCK DIAGRAM
12 x 8 ROM REFERENCE DECODER
7
7
12–BIT
www.lansdale.com
CONTROL LOGIC
÷
R COUNTER
12
ENB
Latch Enable Input (Pin 13)
ister into the latches, and to the programmable counter inputs,
and the switch outputs SW1 and SW2. When low (0), ENB
inhibits the above action and thus allows changes to be made
in the shift register data without affecting the counter program-
ming and switch outputs. An on–chip pull–up establishes a
continuously high level for ENB when no external signal is
applied. ENB is normally low and is pulsed high to transfer
data to the latches.
OSC in , OSC out
Reference Oscillator Input/Output (Pins 19, 18)
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
nected from OSC in to ground and OSC out to ground. OSC in
may also serve as the input for an externally–generated refer-
ence signal. This signal is typically AC coupled to OSC in , but
for larger amplitude signals (standard CMOS logic levels) DC
coupling may also be used. In the external reference mode, no
connection is required to OSC out .
TEST
Factory Test Input (Pin 16)
When high (1), ENB transfers the contents of the shift reg-
These pins form an on–chip reference oscillator when con-
Used in manufacturing. Must be left open or tied to V SS .
10–BIT SHIFT REGISTER
10–BIT
÷
N COUNTER LATCH
A COUNTER BITS
÷
LAST DATA BIT IN (BIT NO. 19)
N COUNTER
10
10
f R
f V
LANSDALE Semiconductor, Inc.
FIRST DATA BIT IN (BIT NO. 1)
N COUNTER BITS
2–BIT SHIFT
DETECTOR
REGISTER
DETECTOR
DETECT
LATCH
PHASE
PHASE
LOCK
B
A
LD
PD out
φ V
φ R
SW2
SW1
Issue A