mc145156 Lansdale Semiconductor, Inc., mc145156 Datasheet - Page 15

• Manufacturer Part Number: mc145156
• Description: Pll Frequency Synthesizer Family
• Manufacturer: Lansdale Semiconductor, Inc.

LANSDALE Semiconductor, Inc.
OUTPUT PINS
PDout
Phase Detector A Output (Pin 6)
signal. Double–ended outputs are also available for this pur-
pose (see φ V and φ R ).
φR, φV
Phase Detector B Outputs (Pins 4, 3)
a loop–error signal. A single–ended output is also available for
this purpose (see PD out ).
leading, then error information is provided by φ V pulsing low.
φ R remains essentially high.
lagging, then error information is provided by φ R pulsing low.
φ V remains essentially high.
φ V and φ R remain high except for a small minimum time
period when both pulse low in phase.
MC
Dual–Modulus Prescale Control Output (Pin 8)
controlling an external dual–modulus prescaler. The MC level-
will be low at the beginning of a count cycle and will remain-
low until the ÷ A counter has counted down from its pro-
grammed value. At this time, MC goes high and remains high-
until the ÷ N counter has counted the rest of the way down-
from its programmed value (N – A additional counts since
both ÷ N and ÷ A are counting down during the first portion of
the cycle). MC is then set back low, the counters preset to their
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Three–state output of phase detector for use as loop–error
Frequency f V > f R or f V Leading: Negative Pulses
Frequency f V < f R or f V Lagging: Positive Pulses
Frequency f V = f R and Phase Coincidence: High–Imped-
These phase detector outputs can be combined externally for
If frequency f V is greater than f R or if the phase of f V is
If the frequency f V is less than f R or if the phase of f V is
If the frequency of f V = f R and both are in phase, then both
Signal generated by the on–chip control logic circuitry for-
ance State
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ML145156
respective programmed values, and the above sequence repeat-
ed. This provides for a total programmable divide value (N T ) =
N • P + A where P and P + 1 represent the dual–modulus
prescaler divide values respectively for high and low MC lev-
els, N the number programmed into the ÷ N counter, and A the
number programmed into the ÷ A counter.
LD
Lock Detector Output (Pin 9)
phase and frequency). LD pulses low when loop is out of lock.
SW1, SW2
Band Switch Outputs (Pins 14, 15)
sponding to data bits numbers one and two. These outputs can
be tied through external resistors to voltages as high as 15 V,
independent of the V DD supply voltage. These are typically
used for band switch functions. A logic 1 causes the output to
assume a high–impedance state, while a logic 0 causes the out-
put to be low.
REF out
Buffered Reference Oscillator Output (Pin 17)
provided reference–input signal.
POWER SUPPLY
V DD
Positive Power Supply (Pin 5)
from + 3 to + 9 V with respect to V SS .
V SS
Negative Power Supply (Pin 7)
ground.
Essentially a high level when loop is locked (f R , f V of same
SW1 and SW2 provide latched open–drain outputs corre-
Buffered output of on–chip reference oscillator or externally
The positive power supply potential. This pin may range
The most negative supply potential. This pin is usually-
ML145156
Issue A