mc145156 Lansdale Semiconductor, Inc., mc145156 Datasheet - Page 18

• Manufacturer Part Number: mc145156
• Description: Pll Frequency Synthesizer Family
• Manufacturer: Lansdale Semiconductor, Inc.

ML145157
INPUT PINS
fin
Frequency Input (Pin 8)
this input decrements the ÷ N counter. This input has an invert-
er biased in the linear region to allow use with AC coupled sig-
nals as low as 500 mV p–p. For larger amplitude signals (stan-
dard CMOS logic levels), DC coupling may be used.
CLK, DATA
Shift Clock, Serial Data Inputs (Pins 9, 10)
data into the on–chip shift registers. The last data bit entered
determines which counter storage latch is activated; a logic
1selects the reference counter latch and a logic 0 selects the
÷ N counter latch. The entry format is as follows:
ENB
Latch Enable Input (Pin 11)
ter into the reference divider or ÷ N latches depending on the
control bit. The reference divider latches are activated if the
control bit is at a logic high and the ÷ N latches are activated if
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Input frequency from VCO output. A rising edge signal on
Each low–to–high transition of the clock shifts one bit of
A logic high on this pin latches the data from the shift regis-
OSC out
REF out
OSC in
DATA
ENB
CLK
f in
PIN DESCRIPTIONS
FIRST DATA BIT INTO SHIFT REGISTER
CONTROL
1–BIT
S/R
ML145157 BLOCK DIAGRAM
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REFERENCE COUNTER LATCH
14–BIT SHIFT REGISTER
14–BIT SHIFT REGISTER
14–BIT
14–BIT
÷
the control bit is at a logic low. A logic low on this pin allows
the user to change the data in the shift registers without affect-
ing the counters. ENB is normally low and is pulsed high to
transfer data to the latches.
OSCin, OSCout
Reference Oscillator Input/Output (Pins 1, 2)
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
nected from OSC in to ground and OSC out to ground. OSC in
may also serve as the input for an externally–generated refer-
ence signal. This signal is typically AC coupled to OSC in , but
for larger amplitude signals (standard CMOS logic levels) DC
coupling may also be used. In the external reference mode, no
connection is required to OSC out .
OUTPUT PINS
PD out
Single–Ended Phase Detector A Output (Pin 5)
duces a loop–error signal that is used with a loop filter to con-
trol a VCO.
φR, φV
Double–Ended Phase Detector B Outputs (Pins 16, 15)
signal. A single–ended output is also available for this purpose
(see PD out ).
N COUNTER LATCH
These pins form an on–chip reference oscillator when con-
This single–ended (three–state) phase detector output pro-
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence:
These outputs can be combined externally for a loop–error
÷
÷
R COUNTER
N COUNTER
High–Impedance State
14
14
14
14
LANSDALE Semiconductor, Inc.
DETECTOR
DETECTOR
DETECT
PHASE
PHASE
LOCK
B
A
f R
LD
PD out
φ V
φ R
f V
S/R out
Issue A