adc1613s NXP Semiconductors, adc1613s Datasheet - Page 13

• Manufacturer Part Number: adc1613s
• Description: Adc1613s Series Single 16-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps; Serial Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
11. Application information
ADC1613S_SER
Product data sheet
11.1.1 Input stage description
11.1.2 Anti-kickback circuitry
11.1 Analog inputs
The analog input of the ADC1613S supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (V
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see
Figure 6
ElectroStatic Discharge (ESD) protection and circuit and package parasitics.
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
Anti-kickback circuitry (RC filter in
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
Fig 6.
shows the equivalent circuit of the sample-and-hold input stage, including
Input sampling circuit
I(cm)
INM
INP
) on pins INP and INM set to 0.5V
All information provided in this document is subject to legal disclaimers.
8
7
Rev. 1 — 14 March 2011
package
Figure
ESD
Single 16-bit ADC; serial JESD204A interface
7) is needed to counteract the effects of a
Section 11.2
parasitics
DDA
.
ADC1613S series
R on = 15 Ω
R on = 15 Ω
internal
internal
switch
switch
and
clock
clock
Table
C s
C s
21).
005aaa185
© NXP B.V. 2011. All rights reserved.
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